Three-input, four-input, eight-input, XNOR and Schmitt NAND gates are on more 74HC gates, and the CMOS equivalents on the CD4000 gates.
Unlike the ideal gate and the ideal inverter,
every chip on this page has real VCC and GND pins and does nothing at all until
they are wired. Unpowered, every output is high impedance, which is the single
commonest reason a logic circuit looks dead on the canvas. Propagation delays come
from each chip's own datasheet and are inertial: a pulse narrower than the delay
never reaches the output, exactly as a real gate's finite output slew swallows a
runt pulse. Aliases: 7400, 7404, 7408, 7432, 7486, 7474, 74595, quad NAND, quad AND,
quad OR, quad XOR, hex inverter, D flip-flop, shift register.
74HC00: quad 2-input NAND gate
The 7400: four independent NAND gates in one 14-pin DIP, pin 7 GND and pin 14
VCC. An input that is unknown or floating still gives a defined output when it
could not change the answer: a 0 on either input of a NAND forces Y high whatever
the other input is doing. Propagation delay: 9 ns typical, from either input to Y.
See it in: NAND latch.
74HC04: hex inverter
The 7404: six independent inverters sharing one supply. Unlike the two-input
packages, it alternates input and output down each row (pin 1 is 1A, pin 2 is
1Y), so its pin table is worth reading against the datasheet rather than assumed
from the 7400. Propagation delay: 9 ns typical. See it in: Traffic light.
74HC08: quad 2-input AND gate
The 7408, same package and pinout as the 74HC00, four AND gates instead of four
NANDs. A 0 on either input forces Y low. Propagation delay: 9 ns typical. See it
in: Full adder.
74HC32: quad 2-input OR gate
The 7432, same package and pinout again, four OR gates. A 1 on either input forces
Y high. Propagation delay: 9 ns typical. See it in: Full adder.
74HC86: quad 2-input XOR gate
The 7486, same package, four exclusive-OR gates: the adder and parity building block, and the cheapest way to make a controllable inverter. An XOR has no controlling value, so any unknown input gives an unknown output. It sits one gate deeper inside the package than a NAND, so it is slower: propagation delay 12 ns typical. See it in: Full adder.
74HC74: dual D-type flip-flop with set and reset
Two independent positive-edge-triggered flip-flops. Each has a data input (nD), a
clock (nCP), an active-low set (nSD) and an active-low reset (nRD), presenting
both nQ and its complement. SD and RD are asynchronous and beat the clock; the
clock only matters on a clean Low-to-High edge, and an edge that arrives while the
supply is still settling is not counted as one, which is what stops a ripple counter
from latching Unknown forever at power-on. A real flip-flop powers up random; this
one powers up cleared (Q low), because a divider fed Unknown would never escape it.
Propagation delay: 14 ns typical, from CP, SD or RD to Q or QN. See it
in: Binary counter.
74HC595: 8-bit shift register with output latch
The chip everyone reaches for when they run out of pins. Two registers inside it:
an eight-stage shift register clocked by SHCP, which moves everything along and
drops DS into stage 0 on a rising edge; and a storage register (the latch), which
is what Q0 to Q7 actually show and which only changes on a rising edge of STCP.
MR (active low) clears the shift register without touching the latch; OE
(active low) three-states the outputs without touching either register, so a
disabled chip still shifts and its last byte is unharmed underneath. Both registers
power up cleared. Propagation delay: 15 ns typical, STCP to Qn. See it in:
LED bar chaser.
Pins
The 74HC00, 74HC08, 74HC32 and 74HC86 share one pinout: inputs first, output third.
| Pin | Name | What it does |
|---|---|---|
| 1, 2 / 3 | 1A, 1B / 1Y |
Gate 1 inputs and output. |
| 4, 5 / 6 | 2A, 2B / 2Y |
Gate 2 inputs and output. |
| 9, 10 / 8 | 3A, 3B / 3Y |
Gate 3 inputs and output. |
| 12, 13 / 11 | 4A, 4B / 4Y |
Gate 4 inputs and output. |
| 7 | GND |
Ground. |
| 14 | VCC |
Supply. |
The 74HC04 alternates input and output:
| Pin | Name | What it does |
|---|---|---|
| 1, 3, 5 | 1A, 2A, 3A |
Inputs; each output is the next pin up (1Y on 2, 2Y on 4, 3Y on 6). |
| 9, 11, 13 | 4A, 5A, 6A |
Inputs; each output is the next pin down (4Y on 8, 5Y on 10, 6Y on 12). |
| 7 | GND |
Ground. |
| 14 | VCC |
Supply. |
The 74HC74:
| Pin | Name | What it does |
|---|---|---|
| 1, 13 | 1RD, 2RD |
Asynchronous reset, active low. |
| 2, 12 | 1D, 2D |
Data. |
| 3, 11 | 1CP, 2CP |
Clock, rising edge. |
| 4, 10 | 1SD, 2SD |
Asynchronous set, active low. |
| 5, 9 | 1Q, 2Q |
Outputs. |
| 6, 8 | 1QN, 2QN |
Inverted outputs. |
| 7 | GND |
Ground. |
| 14 | VCC |
Supply. |
The 74HC595:
| Pin | Name | What it does |
|---|---|---|
| 15, 1 to 7 | Q0, Q1 to Q7 |
The latched outputs. |
| 9 | Q7S |
Serial out, the last shift stage, for chaining the next chip's DS. |
| 10 | MR |
Clears the shift register, active low. Tie it to VCC if unused. |
| 11 | SHCP |
Shift clock, rising edge. |
| 12 | STCP |
Latch clock, rising edge. |
| 13 | OE |
Output enable, active low. Tie it to GND if unused. |
| 14 | DS |
Serial data in. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
The model setting: 74HC, 74HCT or 74LS
The 74HC00, 74HC04, 74HC08, 74HC32 and 74HC86 (and the 74HC02)
each have a model setting that picks which family the chip is built in, on the same
pins with the same logic: for example 74HC00, 74HCT00 or 74LS00.
- 74HC (the default): 2 V to 6 V, inputs switch at half the supply.
- 74HCT: 74HC outputs with TTL input levels, 4.5 V to 5.5 V. Inputs switch at 1.4 V, so a 3.3 V signal reads as a clean high.
- 74LS: low-power Schottky TTL, 4.75 V to 5.25 V. Inputs switch at 1.4 V, an output high sits near 3.4 V (1.6 V under the supply) rather than at the rail, and a floating input reads high, as an open TTL input really does.
The delay is the 74HC figure in every family (the 74LS parts match it within a few
nanoseconds). The 74HC74 and 74HC595 have no model setting: they are 74HC only.
What none of them model
One typical delay, and nothing around it. Each chip carries a single propagation
delay taken from its datasheet's typical column at VCC = 5 V, CL = 15 pF and
25 °C, and uses it for every path through the package. There is no minimum or maximum,
no spread between the gates in one chip, no rise or fall time, no output slew and no
dependence on supply voltage, load capacitance or temperature, all of which a real
74HC part has, and all of which a datasheet gives ranges for. On the 74HC595 the one
figure is the STCP-to-Qn number used for SHCP and MR to Q7S as well, which
the datasheet lists a nanosecond or two apart.
No setup, hold or pulse-width checks. The 74HC74 and the 74HC595 take a clock edge whenever they see one; nothing here refuses data that changed too close to the edge or a clock pulse that was too narrow, and nothing warns about it. A real part would metastable or simply miss.
No supply current, no output current limit and no bus contention damage. An output driving into another output is resolved as two drivers on one net; nothing gets hot.
Sequential parts power up cleared rather than random, because a toggle divider fed Unknown never escapes it. See how faithfully a part behaves.
Common mistakes across the family
Forgetting VCC and GND. Every chip here does nothing at all unpowered, unlike
the ideal gates. And treating a clean but very fast edge as guaranteed to register:
an edge has to cross the threshold once and stay there for the chip's own settling
behavior to count it, the same as on a real HC-family part.
See it in action
NAND latch, Full adder, Traffic light and Binary counter each build a small, real circuit from one of these chips. Browse the whole set at /templates, and read how faithfully a part behaves for why sequential chips here power up cleared rather than random.
Each chip has a part page that draws it live, with its pins and the projects that use it: 74HC00, 74HC04, 74HC08, 74HC32, 74HC86, 74HC74 and 74HC595.