JK flip-flops: 74HC73, 76, 107, 112 and CD4027
The JK flip-flop is the one that can toggle: on a clock edge, J and K decide
whether it holds, clears, sets or flips.
Tie J and K high and it divides its clock by two, which is how counters are
made.
Five chips, two flip-flops each, the same behavior on different pinouts. If a lab sheet just says "dual JK flip-flop", it usually means the 74HC112 (or the 74LS112). Aliases: JK flip flop, J-K flip-flop, 7473, 7476, 74107, 74112, 74LS73, 74LS76, 74LS107, 74LS112, SN74HC112, CD74HC73, CD4027B, HEF4027B, MC14027, toggle flip-flop.
Truth table
On the clock edge (falling on the 74HC parts, rising on the CD4027), J and K as
they were just before it decide:
J |
K |
Q after the edge |
|---|---|---|
| 0 | 0 | Holds |
| 0 | 1 | 0 (clear) |
| 1 | 0 | 1 (set) |
| 1 | 1 | Toggles |
QN is always the complement of Q, except while set and reset are both asserted.
Set and reset (on the chips that have them) are asynchronous: they act at once,
without the clock, and beat it.
74HC73: dual JK flip-flop with reset
Each flip-flop has a clock nCP, nJ and nK, an active-low reset nR, and nQ
and nQN. There is no set. Negative-edge triggered. The supply is not on the
corners: VCC is pin 4 and GND pin 11. Delays: 13 ns from the clock and 12 ns
from the reset, the CD74HC73 typicals at 5 V and 15 pF.
| Pin | Name | What it does |
|---|---|---|
| 1 | 1CP |
Flip-flop 1 clock, falling edge. |
| 14, 3 | 1J, 1K |
Flip-flop 1 J and K. |
| 2 | 1R |
Flip-flop 1 reset, active low. |
| 12, 13 | 1Q, 1QN |
Flip-flop 1 outputs. |
| 5 | 2CP |
Flip-flop 2 clock, falling edge. |
| 7, 10 | 2J, 2K |
Flip-flop 2 J and K. |
| 6 | 2R |
Flip-flop 2 reset, active low. |
| 9, 8 | 2Q, 2QN |
Flip-flop 2 outputs. |
| 11 | GND |
Ground. |
| 4 | VCC |
Supply. |
74HC76: dual JK flip-flop with set and reset
Each flip-flop has a clock nCP, nJ, nK, an active-low set nSD (preset) and an
active-low reset nRD (clear). Negative-edge triggered. The supply is on pins 5
(VCC) and 13 (GND), not the corners. The 74HC76 is no longer made: the model uses
the standard 7476 pinout and takes its delays from the 74HC112, the same flip-flop on
another pinout: 14 ns from the clock, 13 ns from the set and 15 ns from the reset.
| Pin | Name | What it does |
|---|---|---|
| 1 | 1CP |
Flip-flop 1 clock, falling edge. |
| 4, 16 | 1J, 1K |
Flip-flop 1 J and K. |
| 2 | 1SD |
Flip-flop 1 set, active low. |
| 3 | 1RD |
Flip-flop 1 reset, active low. |
| 15, 14 | 1Q, 1QN |
Flip-flop 1 outputs. |
| 6 | 2CP |
Flip-flop 2 clock, falling edge. |
| 9, 12 | 2J, 2K |
Flip-flop 2 J and K. |
| 7 | 2SD |
Flip-flop 2 set, active low. |
| 8 | 2RD |
Flip-flop 2 reset, active low. |
| 11, 10 | 2Q, 2QN |
Flip-flop 2 outputs. |
| 13 | GND |
Ground. |
| 5 | VCC |
Supply. |
74HC107: dual JK flip-flop with reset
The 74HC73's two flip-flops (reset, no set, negative-edge triggered) on a pinout with the supply at the corners. Delays: 14 ns from the clock and 13 ns from the reset, the CD74HC107 typicals at 5 V and 15 pF.
| Pin | Name | What it does |
|---|---|---|
| 12 | 1CP |
Flip-flop 1 clock, falling edge. |
| 1, 4 | 1J, 1K |
Flip-flop 1 J and K. |
| 13 | 1R |
Flip-flop 1 reset, active low. |
| 3, 2 | 1Q, 1QN |
Flip-flop 1 outputs. |
| 9 | 2CP |
Flip-flop 2 clock, falling edge. |
| 8, 11 | 2J, 2K |
Flip-flop 2 J and K. |
| 10 | 2R |
Flip-flop 2 reset, active low. |
| 5, 6 | 2Q, 2QN |
Flip-flop 2 outputs. |
| 7 | GND |
Ground. |
| 14 | VCC |
Supply. |
74HC112: dual JK flip-flop with set and reset
The usual "dual JK flip-flop". Each has a clock nCP, nJ, nK, an active-low set
nSD and an active-low reset nRD. Negative-edge triggered, supply at the corners.
Delays: 14 ns from the clock, 13 ns from the set and 15 ns from the reset, the
CD74HC112 typicals at 5 V and 15 pF.
| Pin | Name | What it does |
|---|---|---|
| 1 | 1CP |
Flip-flop 1 clock, falling edge. |
| 3, 2 | 1J, 1K |
Flip-flop 1 J and K. |
| 4 | 1SD |
Flip-flop 1 set, active low. |
| 15 | 1RD |
Flip-flop 1 reset, active low. |
| 5, 6 | 1Q, 1QN |
Flip-flop 1 outputs. |
| 13 | 2CP |
Flip-flop 2 clock, falling edge. |
| 11, 12 | 2J, 2K |
Flip-flop 2 J and K. |
| 10 | 2SD |
Flip-flop 2 set, active low. |
| 14 | 2RD |
Flip-flop 2 reset, active low. |
| 9, 7 | 2Q, 2QN |
Flip-flop 2 outputs. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
On the 74HC76 and 74HC112, holding set and reset low together drives Q and QN
both high; whichever is released last decides what the flip-flop holds afterwards.
CD4027: dual JK flip-flop with set and reset
The 4000-series JK flip-flop, and different from the 74HC ones in two ways that
matter: it is positive-edge triggered (a rising clock), and its set nS and reset
nR are active high. Both high drives Q and QN high together; whichever is
released last decides what it holds. It runs from 3 V to 18 V, its supply pins are
VDD and VSS, and the pin names are the NXP HEF4027B ones. Delays at 5 V: 150 ns
from the clock, 150 ns from the set and 200 ns from the reset, the CD4027B typicals
at 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 13 | 1CP |
Flip-flop 1 clock, rising edge. |
| 10, 11 | 1J, 1K |
Flip-flop 1 J and K. |
| 9 | 1S |
Flip-flop 1 set, active high. |
| 12 | 1R |
Flip-flop 1 reset, active high. |
| 15, 14 | 1Q, 1QN |
Flip-flop 1 outputs. |
| 3 | 2CP |
Flip-flop 2 clock, rising edge. |
| 6, 5 | 2J, 2K |
Flip-flop 2 J and K. |
| 7 | 2S |
Flip-flop 2 set, active high. |
| 4 | 2R |
Flip-flop 2 reset, active high. |
| 1, 2 | 2Q, 2QN |
Flip-flop 2 outputs. |
| 8 | VSS |
Ground. |
| 16 | VDD |
Supply, 3 V to 18 V. |
Properties
model:
- 74HC73, 74HC76, 74HC107 and 74HC112 offer their 74HC, 74HCT and 74LS versions (for example 74HC112, 74HCT112, 74LS112). The 74LS parts are the A versions (74LS73A, 74LS112A and so on), which are edge triggered like the 74HC ones. The 74HC version runs from 2 V to 6 V and switches at half the supply. The 74HCT version needs 4.5 V to 5.5 V and switches at 1.4 V (TTL levels). The 74LS version needs 4.75 V to 5.25 V, switches at 1.4 V, drives an output high only to about 3.4 V, and reads a floating input as high. Pins, logic and delays are the same in every version: the delays are the 74HC figures.
- CD4027 offers only CD4027B.
What the model gets right
Set and reset are asynchronous and beat the clock. J and K are taken as they were
just before the clock edge, so a flip-flop whose own output feeds its J or K
(as in a counter) behaves. The chip's own power-up is not read as a clock edge.
A clock edge out of an unknown level makes the state unknown, and so does an unknown
J or K, but only where it could change the answer: with Q low, J low and K
floating, the flip-flop stays low either way, and does.
The CD4027 is a 4000-series part: its outputs are weak (about 2000 / VDD ohms, so
400 ohms at 5 V), and its delays shrink as the supply rises, to about half the 5 V
figures at 10 V and about a third at 15 V.
What it does not model
Every flip-flop powers up cleared (Q low), where a real one comes up in
whichever state it falls into. No setup, hold or minimum pulse width checks: a clock
edge counts however close it is to a change on J or K, and data that changes with
the clock is taken as it was before the edge. One delay each from the clock, the set
and the reset, with no dependence on load. The 74HC76 could not be checked against a
74HC76 data sheet; its delays are the 74HC112's.
Common mistakes
Expecting a 74HC JK flip-flop to change on the rising edge: the 74HC73, 74HC76,
74HC107 and 74HC112 move on the falling edge, the CD4027 on the rising one.
Getting set and reset the wrong way up: active low on the 74HC parts, active high on
the CD4027. Leaving them floating: tie unused 74HC sets and resets to VCC and unused
CD4027 ones to VSS. Wiring a 74HC73 or 74HC76 as if its power were on the corners.
See it in action
Browse the example circuits at /templates.