74HC buffers, bus transceiver and comparator
Tri-state buffers, a bus transceiver and an 8-bit comparator: the 74HC125, 126, 244, 245 and 688.
They put a signal onto a shared wire, take it off again, pass a byte between two buses, and check two bytes for equality.
The buffers have tri-state outputs: besides high and low, an output can let go of its wire completely (high impedance, shown as off), so several chips can share one wire as long as only one of them drives it at a time. Aliases: 74125, 74126, 74244, 74245, 74688, SN74HC125, SN74HC244, SN74HC245, 74HCT245, 74LS245, 74LS244, tri-state buffer, line driver, bus transceiver, level shifter, identity comparator.
74HC125: quad tri-state buffer, active-low enables
Four non-inverting buffers, each with its own output enable. With nOE low, nY
follows nA; with nOE high, nY lets go of the net. Propagation delay: 14 ns, the
SN74HC125 typical at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 1, 4, 10, 13 | 1OE to 4OE |
Output enables, active low. |
| 2, 5, 9, 12 | 1A to 4A |
Inputs. |
| 3, 6, 8, 11 | 1Y to 4Y |
Tri-state outputs. |
| 7 | GND |
Ground. |
| 14 | VCC |
Supply. |
nOE |
nA |
nY |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | x | Off |
74HC126: quad tri-state buffer, active-high enables
The 74HC125 with its enables the other way up, on the same pins: with nOE high,
nY follows nA; with nOE low, nY is off. Propagation delay: 14 ns, the
SN74HC126 typical at 4.5 V and 50 pF.
74HC244: octal buffer and line driver
Eight non-inverting tri-state buffers in two groups of four, each group with its own
active-low enable. 1OE low passes 1A1 to 1A4 to 1Y1 to 1Y4; 1OE high
turns those four outputs off. 2OE does the same for the second group. The two
groups face opposite ways on the package, which is why the pin names alternate.
Propagation delay: 13 ns, the SN74HC244 typical at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 1 | 1OE |
Enable for group 1, active low. |
| 2, 4, 6, 8 | 1A1 to 1A4 |
Group 1 inputs. |
| 18, 16, 14, 12 | 1Y1 to 1Y4 |
Group 1 outputs. |
| 19 | 2OE |
Enable for group 2, active low. |
| 11, 13, 15, 17 | 2A1 to 2A4 |
Group 2 inputs. |
| 9, 7, 5, 3 | 2Y1 to 2Y4 |
Group 2 outputs. |
| 10 | GND |
Ground. |
| 20 | VCC |
Supply. |
74HC245: octal bus transceiver
Eight two-way buffers between an A bus and a B bus. The side being driven from is
an input and the other side is an output, and DIR picks which is which.
Propagation delay: 15 ns, the SN74HC245 typical at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 1 | DIR |
Direction. High drives B from A, low drives A from B. |
| 2 to 9 | A1 to A8 |
The A bus. |
| 18 to 11 | B1 to B8 |
The B bus. B1 is pin 18, opposite A1. |
| 19 | OE |
Output enable, active low. High isolates the two buses. |
| 10 | GND |
Ground. |
| 20 | VCC |
Supply. |
OE |
DIR |
What happens |
|---|---|---|
| 0 | 0 | B drives A |
| 0 | 1 | A drives B |
| 1 | x | Both sides off |
The 74HCT245 is the usual way to let a 3.3 V board drive a 5 V bus: powered from 5 V, its TTL input levels read 3.3 V as a clean high.
74HC688: 8-bit identity comparator
Compares two bytes bit for bit. PEQ goes low when P0 to P7 equal Q0 to
Q7 and the enable OE is low; OE high holds PEQ high whatever the bytes are.
It answers "equal or not", not which is bigger (the 74HC85 on the arithmetic
page does that). Two chips make a 16-bit comparator by
wiring the first one's PEQ to the second one's OE. Propagation delay: 30 ns, the
SN74HC688 typical from P or Q at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 2, 4, 6, 8, 11, 13, 15, 17 | P0 to P7 |
First byte. |
| 3, 5, 7, 9, 12, 14, 16, 18 | Q0 to Q7 |
Second byte. |
| 1 | OE |
Enable, active low. |
| 19 | PEQ |
Low when enabled and P equals Q. |
| 10 | GND |
Ground. |
| 20 | VCC |
Supply. |
Pins 2 to 9 and 11 to 18 alternate P and Q: P0 is pin 2 and Q0 is pin 3.
Properties
model: each chip offers its 74HC, 74HCT and 74LS versions (for example 74HC245,
74HCT245, 74LS245). The 74HC version runs from 2 V to 6 V and its inputs switch at
half the supply. The 74HCT version needs 4.5 V to 5.5 V and its inputs switch at
1.4 V (TTL levels). The 74LS version needs 4.75 V to 5.25 V, switches at 1.4 V, drives
an output high only to about 3.4 V, and reads a floating input as high. Pins, logic
and delays are the same in every version: the delays are the 74HC figures.
What the model gets right
An output that is off really lets go of the net, so two buffers on one wire share it properly when only one is enabled, and a pull-up or pull-down on the wire decides the level when none is. Each output is worked out separately, so an unknown input only makes unknown the outputs it could change: a 74HC125 buffer with its enable high is off whatever its input is doing. Delays are each data sheet's typical from data to output, and they are inertial.
What it does not model
One delay per chip: the data sheets give separate, slightly longer enable and
disable times (16 and 17 ns on the 74HC125 and 74HC126, 15 ns on the 74HC244, 23 and
25 ns on the 74HC245, and 16 ns from OE to PEQ on the 74HC688), and the model
uses the data figure for all of them. No damage from two enabled outputs fighting
over one wire: it shows as a conflict on the net, and nothing gets hot. No output
current limit. With more than 12 inputs unknown at once (a chip not wired up yet)
every output is unknown without working out which could be known.
Common mistakes
Getting the enable sense wrong: the 74HC125, 74HC244, 74HC245 and 74HC688 enables are active low, the 74HC126's are active high. Enabling two buffers onto one wire at the same time. Leaving a shared wire with no pull resistor, so it floats whenever every buffer is off. On the 74HC245, forgetting that the side being driven from is an input: leave it floating and the other side shows unknown (or high, on the 74LS version).
See it in action
Browse the example circuits at /templates.