CD4013 dual D flip-flop
Two D flip-flops in one package: on a rising clock edge, Q takes whatever is on
D. Wire QN back to D and the flip-flop divides its clock by two.
It is the 4000-series counterpart of the 74HC74, and the chip behind a great many
hobby circuits: the push-on, push-off switch (a debounced button clocking a
flip-flop with QN on D), frequency dividers and simple memories. Aliases: 4013,
CD4013BE, HEF4013B, MC14013, dual D flip-flop, D-type latch, toggle flip-flop,
divide by two.
It is a 4000-series CMOS part: its supply pins are VDD and VSS, it runs from 3 V
to 18 V, and its outputs are weak (see below).
Pins
| Pin | Name | What it does |
|---|---|---|
| 3 | 1CP |
Flip-flop 1 clock. Q takes D on a rising edge. |
| 5 | 1D |
Flip-flop 1 data. |
| 6 | 1S |
Flip-flop 1 set, active high. |
| 4 | 1R |
Flip-flop 1 reset, active high. |
| 1, 2 | 1Q, 1QN |
Flip-flop 1 outputs. |
| 11 | 2CP |
Flip-flop 2 clock. |
| 9 | 2D |
Flip-flop 2 data. |
| 8 | 2S |
Flip-flop 2 set, active high. |
| 10 | 2R |
Flip-flop 2 reset, active high. |
| 13, 12 | 2Q, 2QN |
Flip-flop 2 outputs. |
| 7 | VSS |
Ground. |
| 14 | VDD |
Supply, 3 V to 18 V. |
Truth table
S |
R |
CP |
Q |
QN |
|---|---|---|---|---|
| 1 | 0 | x | 1 | 0 |
| 0 | 1 | x | 0 | 1 |
| 1 | 1 | x | 1 | 1 |
| 0 | 0 | rising | D |
not D |
| 0 | 0 | anything else | Holds | Holds |
Set and reset act at once, without the clock, and beat it. Both high drives Q and
QN high together; whichever is released last decides what the flip-flop holds
afterwards.
Properties
model: CD4013B, the only choice.
What the model gets right
The outputs are weak. A 4000-series output is a few hundred ohms: the model uses
2000 / VDD ohms, about 400 ohms at 5 V. An LED on an output glows rather than blazes,
and the output voltage sags under the load.
It is slow, and faster on a higher supply. From the CD4013B data sheet's typical
column at 5 V and 50 pF: 150 ns from the clock or the set to Q, 200 ns from the
reset. The delays shrink as the supply rises, to about half at 10 V and about a third
at 15 V.
D is taken as it was just before the clock edge, so wiring QN to D toggles
cleanly, and one flip-flop can feed the next on the same clock. The chip's own
power-up is not read as a clock edge, and a clock edge out of an unknown level makes
the state unknown.
What it does not model
It powers up cleared (Q low), where a real one comes up in whichever state it falls
into. No setup, hold or minimum pulse width checks. One delay each from the clock, the
set and the reset, with no dependence on load.
Common mistakes
Leaving S and R floating: they are active high (unlike the 74HC74's), so tie
them to VSS when you do not need them, or the flip-flop goes unknown. Clocking it
from a bare push button: the contact bounces and the flip-flop toggles several times.
Debounce the button first, for example with an RC and a CD40106 or CD4093 Schmitt
gate.
See it in action
Browse the example circuits at /templates.