74HC adders and comparator
74HC283, 74LS83 and 74HC85: add two 4-bit numbers, or tell which of two 4-bit numbers is bigger, with no clock and no code.
These are the chips of a breadboard calculator or the arithmetic unit of a homemade CPU. Each one chains to the next for wider numbers. Aliases: 74283, 7483, 7485, SN74HC283, CD74HC283, 74LS283, 74LS83A, CD74HC85, 74LS85, 4-bit adder, full adder, binary adder, magnitude comparator.
74HC283: 4-bit binary full adder
Adds two 4-bit numbers, A4 to A1 and B4 to B1, and a carry in, CIN, giving
the sum on S4 to S1 and a carry out on COUT. Bit 1 is the least significant
(the 1s bit), the way the data sheet numbers them, not bit 0. Wire COUT to the next
chip's CIN for an 8-bit adder. Propagation delay: 18 ns, the CD74HC283 typical from
A or B to the sum at 5 V and 15 pF.
| Pin | Name | What it does |
|---|---|---|
| 5, 3, 14, 12 | A1 to A4 |
First number, A1 the 1s bit. |
| 6, 2, 15, 11 | B1 to B4 |
Second number, B1 the 1s bit. |
| 7 | CIN |
Carry in. Tie to GND on the first chip. |
| 4, 1, 13, 10 | S1 to S4 |
The sum, S1 the 1s bit. |
| 9 | COUT |
Carry out: high when the sum is 16 or more. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
The sum and the carry together are a 5-bit number: 9 + 8 with CIN low gives COUT
high and S4 to S1 showing 0001 (17). To subtract, invert B (a 74HC86 with one
input of each gate high does it) and set CIN high.
74LS83: 4-bit binary full adder, 7483 pinout
The same adder as the 74HC283 on the older 7483 pinout, with VCC on pin 5 and
GND on pin 12 instead of the corners. Lab manuals still print it. It was made in
TTL only (there is no 74HC83), so it reads TTL input levels, switching at 1.4 V, its
output high sits near 3.4 V, and a floating input reads high. The carry in is C0
and the carry out C4. Propagation delay: 15 ns, about the order of the 74LS83A data
sheet typicals at 5 V.
| Pin | Name | What it does |
|---|---|---|
| 10, 8, 3, 1 | A1 to A4 |
First number, A1 the 1s bit. |
| 11, 7, 4, 16 | B1 to B4 |
Second number, B1 the 1s bit. |
| 13 | C0 |
Carry in. |
| 9, 6, 2, 15 | S1 to S4 |
The sum, S1 the 1s bit. |
| 14 | C4 |
Carry out. |
| 12 | GND |
Ground. Not a corner pin. |
| 5 | VCC |
Supply, 5 V. Not a corner pin. |
74HC85: 4-bit magnitude comparator
Compares two 4-bit numbers, A3 to A0 and B3 to B0, and raises one of QGT
(A > B), QEQ (A = B) or QLT (A < B). When the two numbers are equal, the cascade
inputs IGT, IEQ and ILT decide, which is how a chain of chips compares wider
numbers: the least significant chip's three outputs go to the next chip's three
cascade inputs. A single chip ties IEQ high and the other two low. Propagation
delay: 16 ns, the CD74HC85 typical from A or B to QGT and QLT at 5 V and
15 pF.
| Pin | Name | What it does |
|---|---|---|
| 10, 12, 13, 15 | A0 to A3 |
First number, A0 the 1s bit. |
| 9, 11, 14, 1 | B0 to B3 |
Second number, B0 the 1s bit. |
| 4 | IGT |
Cascade in: A > B from the stage below. |
| 3 | IEQ |
Cascade in: A = B from the stage below. |
| 2 | ILT |
Cascade in: A < B from the stage below. |
| 5 | QGT |
High when A > B. |
| 6 | QEQ |
High when A = B. |
| 7 | QLT |
High when A < B. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
Truth table
The 74HC85:
| A vs B | IGT |
ILT |
IEQ |
QGT |
QLT |
QEQ |
|---|---|---|---|---|---|---|
| A > B | x | x | x | 1 | 0 | 0 |
| A < B | x | x | x | 0 | 1 | 0 |
| equal | x | x | 1 | 0 | 0 | 1 |
| equal | 1 | 0 | 0 | 1 | 0 | 0 |
| equal | 0 | 1 | 0 | 0 | 1 | 0 |
| equal | 1 | 1 | 0 | 0 | 0 | 0 |
| equal | 0 | 0 | 0 | 1 | 1 | 0 |
The last two rows are what the data sheet prints for cascade inputs no chain would give, and the model follows it.
Properties
model:
- 74HC283 and 74HC85 offer their 74HC, 74HCT and 74LS versions (74HC283, 74HCT283, 74LS283; 74HC85, 74HCT85, 74LS85). The 74HC version runs from 2 V to 6 V and switches at half the supply. The 74HCT version needs 4.5 V to 5.5 V and switches at 1.4 V. The 74LS version needs 4.75 V to 5.25 V, switches at 1.4 V, drives an output high only to about 3.4 V, and reads a floating input as high. Pins, logic and delay are the same in every version: the delay is the 74HC figure.
- 74LS83 offers only 74LS83.
What the model gets right
Each output is worked out separately, so an unknown input only clouds the outputs it
could change: adding a number with a floating 8s bit to 0 leaves S1 to S3 known.
Delays are each data sheet's typical (the 74LS83's an approximation to them), and
they are inertial.
What it does not model
One delay per chip for every path. The data sheets give others: on the 74HC283 the
carry in to the sums is 13 to 19 ns and to COUT 16 ns; on the 74HC85 A or B to
QEQ is 14 ns and the cascade inputs 9 to 11 ns. So a chain of adders settles in one
step here, where a real ripple of carries takes a little longer per chip, and there
are no glitches on the sum while it settles.
Common mistakes
Numbering the adder bits from 0: on the 74HC283 and 74LS83 the 1s bit is A1, B1
and S1. Wiring a 74LS83 as if it had its power on the corners like a 74HC283.
Leaving CIN or the 74HC85's cascade inputs floating: on a lone 74HC85, IEQ goes to
VCC and IGT and ILT to GND, or QEQ never goes high.
See it in action
Browse the example circuits at /templates.