How faithfully a part behaves

What "analog islands solved by nodal analysis, digital everywhere else" means when you are the one wiring it.

Mokxi says on every screen that it solves analog islands by nodal analysis and runs everything else on a digital path. Here is what that buys you on the canvas and what it costs you. A SPICE deck is another matter: it runs on Mokxi's SPICE engine, which has the analyses and models this page says the canvas lacks (SPICE netlists).

What the engine actually does

Every part that drives a net does so as a voltage behind a source impedance. A net settles to the impedance-weighted mean of whatever is driving it, and its logic level comes from the lowest-impedance driver. Two drivers of equal strength disagreeing gives Unknown. Nothing driving at all gives Floating. A chip or board pin driving push-pull does it through 30 ohms, which is about what a real CMOS output is, but there is no current limit behind it: a pin here will pass whatever the rest of the circuit asks for and never latch up, shut down or get hot.

The kernel is event driven: it resolves a net and then wakes only the parts that saw a change. That is why a few hundred parts run at real time in a browser tab, and why an idle circuit costs almost nothing.

A part whose behavior is a differential equation over several nodes at once, such as a capacitor, an inductor, an op-amp or a signal generator, pulls every net it touches into an analog island, and that island is solved as one matrix by modified nodal analysis: an operating point at power-on, then a transient with trapezoidal integration and a step chosen from the local truncation error. The step shrinks through a fast edge, grows again in a quiet stretch, and lands on a source's corner rather than integrating across it. Where the trapezoidal rule would ring, a few steps of Gear 2 damp it instead; the analysis article says how that is decided and what it costs. A digital pin on the edge of an island goes into the matrix as one voltage behind one source impedance, and the island hands its answer back to the rest of the circuit the same way, so a board full of logic pays nothing for the analog corner of it.

What that means at the bench

Digital is right. Logic levels, thresholds, propagation delays, timer periods, PWM frequencies, interrupt latency, serial baud timing: all of it comes from the datasheet and behaves the way the chip does. A 74HC00 that is not powered really does sit high impedance. A pulse narrower than a chip's propagation delay really is swallowed.

Passives are solved, not guessed. A resistor is Ohm's law with no special cases, which is enough to be a pull-up, a pull-down, a divider and an LED's current limiter, and it joins an island that reaches it rather than making one. A capacitor or an inductor is in the matrix, so an RC network lands on the true exponential and a 555's astable keeps time to a twentieth of a percent of the formula, measured at three decades of timing resistor.

An LED is a diode, and the diode is the real equation. Since 17 September 2026 a diode, an LED, a seven-segment die and a transistor are device physics rather than a number written down:

part	model	what sets it
diode	Shockley, I = Is (exp(Vj / (N Vt)) - 1), with a bulk series resistance	the model card, or forward read as the drop at 10 mA
zener	the same, plus SPICE's BV / IBV / NBV reverse breakdown term	the model card's Vz at Izt with Zzt ohms there, or vz and izt
led, sevenseg, rgbled	the same equation, with N = 2 and 12 ohm of bulk	the color's drop at 20 mA: red 1.8 V, yellow 2.0, green 3.0, blue 3.0, white 3.1
transistor	Ebers-Moll in its transport form, with an Early voltage	the model card, beta, and the vbe and vce_sat overrides
transistor (TIP120)	two of those on one die with the package's own bleed resistors and reverse diode	the pair's own card; see the table below
mosfet	level 1 Shichman-Hodges, with the body diode	the model card, or vto, beta and lambda
opamp	a voltage-controlled voltage source with one dominant pole, a slew rate, headroom short of each rail, an input offset and an output current limit	the model card (rail-to-rail, 741, TL072, LM358), and gain, gbw, slew, headroom, offset, ilimit and negative

So there is no forward drop anywhere in the code. A 1N4148 drops 0.62 V at a milliamp and 0.68 V at four, because that is what the curve does; a red LED on 5 V through 220 ohm passes 14.9 mA rather than the 13.6 mA a 1.8 V drop would give; and a transistor's Vbe is whatever its base current makes it, near 0.63 V at a milliamp. A transistor bottoms out because its collector junction goes forward and the reverse transport current eats the forward one, which is what saturation is, rather than because a floor was written into the part.

The brightness you see is still a short average of the current with a time constant near 8 milliseconds, which is roughly what your eye does, so a PWM-dimmed LED looks dimmed rather than flickering.

The same model is used whether or not the part is in a matrix. A diode with a capacitor near it is stamped into the island and solved by Newton-Raphson with everything else; a diode on its own solves the one loop through itself, against the same equation. There are not two models to disagree. What only the island has is time: a part off any island is solved at DC, so its junction capacitance (below) does nothing until something puts it on an island.

Every model card, and where each number came from

This is the whole device library, parameter by parameter, with the datasheet each number was taken from and how far it is from being a measurement. Three words are used and they mean exactly what they say:

• verified: the number is printed on the datasheet, or falls directly out of a figure that is. It has been checked against the equation by hand and, where ngspice can express the same card, against ngspice 42 within 1 %.
• derived: the number is not on the datasheet, but it is fixed by numbers that are: a saturation current from a forward voltage at a current, a beta from an Rds(on) at a gate voltage, a BV from Vz and Zzt. The arithmetic is in the module doc of the part's own source file.
• assumed: the number is a judgment. A datasheet does not give it, nothing on the datasheet fixes it, and it has been chosen to be plausible for the part and marked here rather than hidden.

Diodes: diode

Shockley with a bulk series resistance. Reverse breakdown is in the junction model but none of these cards names one, so a diode driven past its reverse rating stays off rather than avalanching; that is zener's job.

model	Is	N	Rs	source	standing
1N4148	4.352 nA	1.906	0.6458 Ω	Vishay 1N4148 forward characteristics	derived from two points on the forward curve
1N4007	7.028 nA	1.808	0.0342 Ω	Vishay 1N4007 forward characteristics	derived, same way
1N5817	1.0 µA	1.05	0.075 Ω	ON Semi 1N5817 VF at 100 mA and 1 A	Is/Rs derived from those two points; N assumed
1N5819	30 nA	1.05	0.05 Ω	ON Semi 1N5819 VF	derived; N assumed
BAT54	100 nA	1.05	0.75 Ω	Nexperia BAT54 VF at 10 mA and 100 mA	Is/Rs derived; N assumed

And their capacitance, since Analog 3

Every diode card now carries a junction capacitance and, where the junction stores charge, a transit time. A datasheet prints a capacitance at a stated reverse bias; Cjo = C(vr) (1 + vr/Vj)^M runs that back to the zero-bias value the model wants.

model	datasheet capacitance	Cjo	Vj, M	trr	TT
1N4148	4 pF at VR = 0	4 pF	0.7 V, 0.33	4 ns at 10 mA	5.77 ns
1N4007	15 pF at VR = 4 V	28.1 pF	0.7 V, 0.33	2 µs, assumed	2.885 µs
1N5817	450 pF at VR = 1 V	779 pF	0.5 V, 0.5	none	0
1N5819	150 pF at VR = 4 V	450 pF	0.5 V, 0.5	none	0
BAT54	10 pF at VR = 1 V	17.3 pF	0.5 V, 0.5	none	0

parameter	standing
the datasheet capacitance and the bias it was measured at	verified
Cjo	derived from it through the junction law
Vj and M	assumed: no diode datasheet prints either. 0.7 V and 0.33 for a silicon pn junction, 0.5 V and 0.5 for a Schottky's metal-silicon barrier
TT for the 1N4148	derived from the datasheet's trr, where trr = TT ln(1 + If/Ir) and the datasheet measures at equal currents, so trr = TT ln 2
TT for the 1N4007	assumed: the 1N400x datasheet does not print a reverse recovery time at all, and 2 µs is the figure the family is generally quoted at
TT for the three Schottkys	zero, and that is the physics. A Schottky is a majority-carrier device: there is no stored minority charge to sweep out and therefore no reverse recovery. It is the reason to put one in a supply, and a student can now see it by putting a 1N4148 and a 1N5819 through the same switching circuit

Two approximations to know about. The capacitance sits across the whole part rather than behind Rs, which leaves out an Rs·Cj pole of a few picoseconds. And the engine's step will not go below 100 nanoseconds unless you ask it to, so a 4 ns recovery is in the model and invisible at the default step; set a finer step in the analysis sheet to see it.

A Schottky datasheet does not print an emission coefficient, so N = 1.05 is the assumption in all three; it is what makes the metal-silicon junction softer than a pn one, and the two forward points then fix the other two numbers exactly.

Zeners: zener, 1N4728A to 1N4742A

parameter	source	standing
Vz, Izt, Zzt	ON Semi 1N4728A–1N4764A, Electrical Characteristics	verified, all fifteen parts
BV, IBV, Rs	BV = Vz - Izt Rs, IBV = Izt, Rs = Zzt - Vt / Izt	derived from those three
NBV	none	assumed: 1, SPICE's default, an avalanche knee rather than a soft one
Cjo	assumed: 3 nF·V / Vz, with Vj = 0.7 V and M = 0.5. The 1N4728A–1N4742A datasheet prints a typical capacitance that runs from over a nanofarad on the 3.3 V part to a couple of hundred picofarads on the 12 V one, and does not print one per part; this law is fitted to the shape of that curve and is not a datasheet number for any individual card
TT	not modeled: zero. A Zener's stored charge coming out of avalanche is not a number any of these datasheets gives
forward Is = 3.8 nA, N = 1.7	the datasheet gives one forward point (VF ≤ 1.2 V at 200 mA) and no curve	assumed

Bipolar transistors: transistor

Ebers-Moll in transport form. Vaf (the Early voltage) and Br (the reverse gain) are assumed on every card: neither is on a small-signal datasheet, and both are read off an output-characteristic curve by whoever builds the model.

model	type	Bf	Is	Br	Vaf	source and standing
2N2222	NPN	100	14.34 fA	6.0	74 V	ON Semi 2N2222A; Bf verified (hFE typ), Is derived from VBE(on), rest assumed
BC547	NPN	200	18.0 fA	6.0	80 V	Nexperia BC547B; Bf verified, Is derived, rest assumed
BC548	NPN	200	18.0 fA	6.0	80 V	the BC547's card, the same die; what separates them is the VCEO rating, 30 V against 45, and nothing here models a breakdown rating
2N3904	NPN	150	6.734 fA	0.7371	74 V	ON Semi 2N3904; Bf verified, Is derived, rest assumed
2N3906	PNP	150	1.41 fA	4.977	18.7 V	ON Semi 2N3906; same standing
2N2907	PNP	200	1.8 pA	4.0	115 V	ON Semi 2N2907A; Bf verified (hFE typ at 150 mA), Is derived from VBE(on) = 0.65 V at 150 mA, rest assumed
BC557	PNP	200	18.0 fA	6.0	80 V	Nexperia BC557B; same standing

And their capacitance, since Analog 3

This is what gives a transistor a high-frequency corner and a common-emitter stage its Miller effect. Before Analog 3 a transistor here was flat to any frequency you could name, and the AC article said so.

Three numbers off every small-signal transistor datasheet do it: Cibo, the input capacitance with the output shorted, which is the base-emitter junction; Cobo, the output capacitance with the input open, which is the base-collector junction; and fT, the transition frequency.

model	Cibo at VEB	Cobo at VCB	fT	TF
2N2222	25 pF at 0.5 V	8 pF at 10 V	300 MHz	531 ps
BC547, BC548	11 pF at 0.5 V	6 pF at 10 V	300 MHz	531 ps
2N3904	8 pF at 0.5 V	4 pF at 5 V	300 MHz	531 ps
2N3906	10 pF at 0.5 V	4.5 pF at 5 V	250 MHz	637 ps
2N2907	30 pF at 0.5 V	8 pF at 10 V	200 MHz	796 ps
BC557	11 pF at 0.5 V	6 pF at 10 V	150 MHz	1.06 ns

parameter	standing
Cibo, Cobo, fT and the biases	verified, off the datasheet
Cje, Cjc	derived from those through the junction law
TF	derived: fT = 1/(2π(TF + (Cje+Cjc)/gm)), and at the current a datasheet measures fT at the TF term dominates, so TF ≈ 1/(2π fT)
Vje, Vjc = 0.75 V and Mje, Mjc = 0.33	assumed: no transistor datasheet prints a grading coefficient. They are the textbook pair for a diffused silicon junction
TR, the reverse transit time	not modeled: zero on every card. It only matters to a transistor coming out of hard saturation

Measured: a 2N2222 common-emitter stage biased 47 k/10 k off 10 V with 4.7 k on the collector rolls off at 8.93 MHz, which is inside ngspice 42's own bracket for the same card, and the whole Bode plot agrees with ngspice to 0.0001 dB over six decades. Double the collector resistor and the corner falls, because the gain multiplies Cjc. That is the Miller effect, and it is there because Cjc is between the input and the output rather than a capacitance to ground.

The Darlington: transistor, model TIP120

Not one transistor with a big gain: two transistors, the two bleed resistors the package really has, and the reverse diode across it, with the node between the pair solved inside the device rather than given to the matrix.

parameter	value	source and standing
R1 (base to the internal node)	8 kΩ	ST TIP120 internal schematic: verified
R2 (internal node to emitter)	120 Ω	same: verified
reverse diode	Is = 10 pA, N = 1.6, Rs = 0.05 Ω	the package has one; its curve is assumed
driver Is / Bf	10 fA / 60	assumed
output Is / Bf	1 pA / 40	assumed, chosen so the pair gives the datasheet's minimum hFE of 1000 at an amp
Br = 5, Vaf = 100 V, both	none	assumed

What falls out of it is the part of a Darlington worth teaching, and it is checked against ngspice 42 running the same two transistors and two resistors: the base sits at 1.464 V (two junctions, not one), the collector bottoms out at 0.741 V and no lower, because the output transistor's collector is tied to the driver's and cannot go below the driver's own Vbe, and the gain collapses to tens at a milliamp because R1 takes the base current instead.

MOSFETs: mosfet

Level 1 Shichman-Hodges, with the body diode the bulk-to-source bond really is.

model	channel	Vto	beta	lambda	body VSD at IS
2N7000	N	1.824 V	0.1571 A/V²	0.02	1.5 V at 0.2 A
IRLZ44N	N, logic level	1.5 V	12.99 A/V²	0.01	1.2 V at 24 A
IRF540N	N	3.0 V	3.25 A/V²	0.01	1.3 V at 33 A
BS250	P	−2.4 V	0.0094 A/V²	0.02	1.5 V at 0.5 A
IRF9540N	P	−3.0 V	1.221 A/V²	0.01	2.0 V at 19 A

parameter	source	standing
Vto	the middle of the datasheet's VGS(th) band	verified
beta	whatever makes 1 / (beta (Vgs − Vto)) the datasheet's Rds(on) at the gate voltage it is quoted at	derived
lambda	none	assumed
body diode VSD at IS	the datasheet's source-drain point (Infineon IRLZ44N, IRF540N, IRF9540N; ON Semi 2N7000; Vishay BS250)	verified for the power parts; the 2N7000's and BS250's are the datasheet maximum rather than a typical, so those two are pessimistic
body diode Is, Rs	that point plus an assumed 0.75 V at a hundredth of IS, with N = 1	derived from one verified point and one assumption

An IRLZ44N from a 5 V gate is 0.022 Ω, which is the datasheet's own number at five volts and the whole reason a logic-level part exists; an IRF540N on the same gate is seven times worse, because its number is quoted at ten.

And their capacitance, since Analog 3, with one thing it does not have

A MOSFET gate now takes charge, so it takes time to turn on. Three numbers off every MOSFET datasheet do it, all quoted together at VDS = 25 V:

model	Ciss	Coss	Crss	Cgs = Ciss−Crss	Cgd = Crss	body Cjo from Coss−Crss
2N7000	60 pF	25 pF	5 pF	55 pF	5 pF	121 pF
IRLZ44N	1750 pF	250 pF	120 pF	1630 pF	120 pF	787 pF
IRF540N	1960 pF	250 pF	40 pF	1920 pF	40 pF	1.27 nF
BS250	55 pF	30 pF	12 pF	43 pF	12 pF	109 pF
IRF9540N	1400 pF	400 pF	200 pF	1200 pF	200 pF	1.21 nF

parameter	standing
Ciss, Coss, Crss and the VDS	verified, off the datasheet
Cgs, Cgd	derived: Crss is the gate-drain capacitance and Ciss − Crss is the gate-source one
Cgb	zero, and that is the part. On a three-legged discrete MOSFET the bulk is bonded to the source, so what would be gate-bulk capacitance is already inside Cgs
the body diode's Cjo	derived from Coss − Crss at 25 V through the junction law, with Vj = 0.7 V and M = 0.5 assumed (an abrupt junction, which is what a body diode is)

The approximation, named: this is the constant-overlap model, not Meyer. Cgs and Cgd are constants. That is the same thing ngspice's level 1 computes when a card gives overlap capacitances and no oxide thickness, and the two agree to 0.03% on an IRLZ44N's gate charge to 5 V: 13.424 µs against ngspice's 13.420 µs at a milliamp-equivalent drive.

What it does not have is the Miller plateau. On a real power MOSFET Crss climbs by more than an order of magnitude as the drain falls towards zero, which holds the gate at a plateau while the drain swings and makes the datasheet's total Qg several times the linear Ciss · Vgs this model gives. An IRLZ44N's datasheet Qg is 48 nC at a 10 V gate; this model's is about 17 nC. So: the turn-on time constant is right, the switching energy is optimistic, and a circuit whose point is the Miller plateau is not one to study here yet. A voltage-dependent Cgd is on the phase 2 list in docs/analog-3.md.

The op-amp: opamp

A single-pole macromodel with four cards. Every number property at zero means the card's value, the way a diode's forward does; offset and negative are properties of the circuit rather than of the part and default to zero.

parameter	rail-to-rail (default)	741	TL072	LM358	standing
gain, open-loop	100 000	200 000	200 000	100 000	datasheet typical for the part numbers; the default's is the old ideal part's, "high enough that feedback decides"
gbw, gain-bandwidth	10 MHz	1 MHz	3 MHz	0.7 MHz	datasheet typical; the default's is assumed
slew	none	0.5 V/µs	13 V/µs (not resolved, see below)	0.3 V/µs	datasheet typical
headroom, top / bottom	0 / 0 V	1.5 / 1.5 V	1.5 / 1.5 V	1.5 / 0.005 V	derived from the datasheet swing at a light load; one number at any load
ilimit, short circuit	25 mA	25 mA	40 mA	40 mA	datasheet typical for the 741 and LM358, assumed for the TL072 and the default; the same sourcing and sinking
output resistance	100 Ω	75 Ω	100 Ω	100 Ω	datasheet for the 741, assumed for the rest
offset	0 mV	0 mV	0 mV	0 mV	a property: a real part's offset is a spread, not a value
negative	0 V	0 V	0 V	0 V	a property: how far below the GND pin the output may swing. V- is modeled as a number, not a pin; see below

The pole. One dominant pole at gbw / gain makes the open-loop gain fall at 20 dB a decade and reach one at the gain-bandwidth product, which is the whole of a datasheet's Bode plot below a few megahertz. It is integrated with backward Euler whatever method the rest of the island is on: a closed-loop pole is gain times faster than the open-loop one, which is stiff against any step the solver takes, and the trapezoidal rule rings on a stiff pole at every step longer than its time constant. The pole is also a state the step controller watches, so a step response is drawn at the resolution it asks for. Measured against its own closed form (crates/analog/tests/opamp.rs): a 741's open-loop pole at 5.000 Hz, unity gain at 1 MHz with 90.0 degrees of lag, a non-inverting gain of 11 3 dB down at 90.85 kHz against GBW / 11 = 90.91 kHz, and a unity-gain buffer at 1.000 MHz.

The clamps. Rails, slew and current limit are modes the solver picks after each solve, not Newton iterations: linear, at the top rail less its headroom, at the bottom rail plus its headroom, slewing, or a current source at the limit. A saturated op-amp holds its pole at the rail rather than winding it up, so it comes out of saturation from the rail.

Why V- is a property. The part has five pins (IN+, IN-, OUT, V+, GND) and no V-, and it will not grow one: adding a pin changes the part's shape for every circuit already saved with it. What was actually missing was not the pin but the swing, so the negative rail is the negative property: how many volts below the GND pin the output may go. Leave it at zero and the part is the single-supply op-amp it always was. Set it to 9 and a textbook inverting amplifier about ground works the way the page a student is copying from draws it.

What that is a model of, exactly: a split supply whose midpoint is the GND pin. The current the output sinks while it is below ground returns through the GND pin, because there is nowhere else for it to go, so a meter in the ground leg here reads a current a real split-supply circuit would find in its V- leg. A circuit that needs a negative rail for something other than the op-amp's own output still cannot be built.

What a slew rate can and cannot show. It is a limit on how far the output moves in one integration step, which is the only place a speed lives in a transient, so it can only bind while the step is short enough to see it. A part whose model has a slew rate holds its island to a step of about ten microseconds, two hundred times finer than the kernel's own ceiling, and that is why the default model has none. A part that would cross its own swing in less than one of those steps is not rate limited at all: on a 5 V supply that is anything above about half a volt a microsecond. A 741's 0.5 V/µs is modeled. A TL072's 13 V/µs is not: its edges are set by its 3 MHz pole instead.

What is approximated, on purpose

Every device here leaves things out, and the list is short and specific:

• Temperature is fixed at 27 C. Every junction, always. A real diode's drop moves about 2 mV a degree and a real transistor's beta climbs with heat; neither happens here.
• Junction capacitance is in, and it has named gaps. Every diode, LED and Zener card carries a junction capacitance, and the 1N4148 and 1N4007 carry the transit time that gives them a reverse recovery. Every single-transistor card carries Cje, Cjc and TF, so a transistor has a high-frequency corner and a common-emitter stage has its Miller effect. Every MOSFET card carries a gate capacitance, so a gate takes charge and time to turn on. What is still missing, part by part, is in the tables above: no reverse transit time TR on a transistor, a constant Cgd and so no Miller plateau on a MOSFET, no stored charge on a Zener or an LED, and no capacitance at all on the TIP120 Darlington, which still switches in nothing flat.
• No reverse breakdown on an ordinary diode. The junction model has it (SPICE's BV and IBV) and the Zener is built on it, but no diode card names one, so a rectifier driven past its reverse rating stays off instead of avalanching.
• No high-level injection. A transistor's beta does not fall off at high current, so a saturation voltage at hundreds of milliamps comes out lower than the datasheet's figure at the same current.
• The MOSFET's body diode is modeled and its reverse recovery is not. It has a junction capacitance and no transit time, so it conducts the moment the drain goes a diode drop the wrong side of the source, which is what protects a half bridge and what a battery put in backwards finds, but it turns off with no stored charge to sweep out, and that is the one number a bridge designer actually wants from it. There is still no sub-threshold conduction: below Vto the channel is exactly off, where a real one is exponentially nearly off.
• Level 1 is honest for a switch and optimistic for an amplifier. It has no short-channel behavior, so a MOSFET amplifier's gain comes out high.
• Nothing has a thermal limit. See "Nothing is destroyed", below.

The devices are verified against the equations by hand and against ngspice 42 on the same model cards: a diode's operating point, an LED through a resistor, a common-emitter bias point, a MOSFET switch, both new Schottky cards, a Zener regulator loaded and unloaded, a logic-level MOSFET and its body diode, a P-channel power MOSFET on the high side, and a Darlington against the two transistors and two resistors it is made of, all within 1 %. The hand solutions and the numbers ngspice printed are written into crates/analog/tests/devices.rs so a reader can check them with a calculator.

The capacitances are held the same way, in crates/analog/tests/caps.rs, by running ngspice 42 on the same deck whenever it is installed: a common-emitter Bode plot that agrees to 0.0001 dB, an IRLZ44N's gate charging to 5 V in 13.424 µs against ngspice's 13.420, and a 1N4148's reverse recovery peak of 13.32 mA against 13.28. A machine without ngspice skips those comparisons and says so rather than passing them quietly.

The op-amp is the one device with no ngspice card of its own, because it is not a device: its rail clamp is compared against a table-limited E source, which is the same four numbers, and its pole, slew rate, headroom and current limit are held to their closed forms. The SPICE export writes the same macromodel as a subcircuit, and a gain-of-11 741 amplifier exported and run in ngspice has its corner within 1% of Mokxi's own.

What the analyses will and will not tell you

The analyses a SPICE user reaches for first are here, in Analysis… in the more menu and on Shift+O, and the analysis article is the full account of each:

• the DC operating point, every node's voltage and every analog part's current at once;
• a DC sweep and a parameter sweep, one property of one part stepped over a range with the operating point taken at each value;
• a small-signal AC analysis with a Bode plot, gain and phase from one source to one net over a log sweep, taken about the bias the circuit is holding. Because the devices now have their capacitance, a transistor stage rolls off on its own rather than staying flat to any frequency.

Each one is narrower than its SPICE namesake, and the article says how:

• the operating point is the one the circuit powers on at, capacitors discharged, not SPICE's .op with every capacitor open;
• every point of a property sweep is a cold start with no continuation from the point before, so a capacitor is discharged at every point unless you ask each point to settle;
• the AC analysis drives one source, and the source, the input and the output all have to be on the same analog island;
• a sweep or a frequency response takes at most 1001 points.

And some analyses are not on the canvas at all. A live circuit will not show you:

• noise, or temperature,
• distortion or the spectrum of a waveform,
• a transfer function with its input and output impedance,
• a sweep through a transient rather than through an operating point,
• parasitic inductance and capacitance nobody drew.

An op-amp is a single-pole macromodel: a gain-bandwidth product, a slew rate, headroom, an offset and a current limit, but no bias current, no input resistance, no common-mode range and no second pole. So in a frequency response an active filter rolls off where its op-amp runs out of gain as well as where its capacitors say, but an op-amp's phase margin is never in question.

If you need those, write the circuit as a SPICE deck and run it with Run a SPICE deck…: it has noise, temperature, .tf and .meas, and full device cards. Distortion analysis and parasitics nobody drew are not there either; for those you want LTspice or ngspice, and the product says so rather than guessing.

Nothing is destroyed

There is no smoke. Put a bare wire from a 5 V rail to an LED and it lights, and the probe reports a current a real LED would not survive. That is on purpose: a mistake you can see on the readout teaches more than a part that vanishes.

The same choice runs right through: no part has a current, voltage or power rating, no supply rail sags, and no pin has a limit. So there are real projects that work here and fail on the bench: a servo stalling on the board's regulator, a long WS2812 strip at full white, a relay coil and a motor sharing one supply. Mokxi will grade the wiring. It will not grade the power budget.

Sequential chips power up cleared

A real flip-flop powers up at random, and an honest model would start it Unknown. But a toggle divider fed Unknown never escapes it, so nothing built from flip-flops would ever run without an explicit reset. The 74HC74 and the 74HC595 therefore power up cleared. Unknown still comes from genuinely unknown inputs and from clock edges the model does not trust.

The whole story

What Mokxi simulates is the engine's own contract document: the impedances, the thresholds, the timing wheel and the component interface every part is written against. It is the same file the engineers build to.