74HC193 up/down counter
A 4-bit binary counter that counts both ways, with a separate clock for each direction.
There is no up/down pin: a rising edge on CPU counts up, a rising edge on CPD
counts down, and the clock you are not using has to sit high. Aliases: 74193,
SN74HC193, CD74HC193, up/down counter, presettable counter.
Pins
| Pin | Name | What it does |
|---|---|---|
| 5 | CPU |
Count-up clock. |
| 4 | CPD |
Count-down clock. |
| 3, 2, 6, 7 | Q0 to Q3 |
The count, Q0 the 1s bit. |
| 15, 1, 10, 9 | D0 to D3 |
The number PL loads. |
| 11 | PL |
Parallel load, active low. Low loads D0 to D3 at once. |
| 14 | MR |
Master reset, active high. High clears the count and beats everything. |
| 12 | TCU |
Carry, active low: low while the count is 15 and CPU is low. |
| 13 | TCD |
Borrow, active low: low while the count is 0 and CPD is low. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply, 2 V to 6 V. |
Truth table
MR |
PL |
CPU |
CPD |
What happens |
|---|---|---|---|---|
| 1 | x | x | x | Clear to 0 |
| 0 | 0 | x | x | Load D0 to D3 |
| 0 | 1 | rising | 1 | Count up (15 goes to 0) |
| 0 | 1 | 1 | rising | Count down (0 goes to 15) |
To count past 15, wire TCU to the next chip's CPU and TCD to its CPD. The carry
rises as the count rolls over, and that rising edge is the next chip's clock.
Properties
None.
What the model gets right
The load and the reset are asynchronous (they do not wait for a clock), and the
carry and borrow go low only for the second half of the clock pulse that is about to
roll the count over, as the data sheet describes. Delays are the CD74HC193 typicals
at 5 V and 15 pF: 18 ns from a clock or PL to the count, 17 ns from MR, and 10 ns
to TCU and TCD.
Inside the chip the two clocks meet in an AND gate and the counter moves on its
rising edge, and the model does the same: a pulse on CPU while CPD is held low
counts nothing, and CPD coming back up afterwards counts down. That is also why
moving a direction switch can make one count of its own.
What it does not model
No setup or hold times, no minimum time between the two clocks, and one delay per path with no dependence on supply or load. It powers up at 0.
Common mistakes
Tying the unused clock low: the counter then never counts.
Leaving MR floating; it is active high, so tie it to GND. And PL is active low,
so tie it to VCC.
See it in action
Up/down counter steers a clock into CPU or CPD with a 74HC02 and a slide switch,
and shows the count on four LEDs. Open it at /templates.