CD4000 logic gates

The 4000-series CMOS gates, buffers and Schmitt triggers: the chips in most hobby electronics books and kits that run from a 9 V battery.

CD4001, CD4011, CD4071, CD4081, CD4070, CD4030, CD4077, CD4002, CD4012, CD4023, CD4025, CD4069, CD4049, CD4050, CD4093 and CD40106.

They do the same logic as the 74HC gates, with three differences that follow from being 4000-series parts:

• They run anywhere from 3 V to 18 V, and their supply pins are called VDD and VSS. Inputs switch at half the supply.
• Their outputs are weak. A 4000-series output is a few hundred ohms: the model uses 2000 / VDD ohms, about 400 ohms at 5 V and 200 ohms at 10 V, from the CD4011B data sheet's output currents. One drives an LED only dimly without a transistor, and its output voltage sags under load.
• They are slow, and faster on a higher supply. Each delay is the data sheet's typical at 5 V and 50 pF, scaled with the supply the way the CD4011B's 5, 10 and 15 V figures fall: 0.48 of the 5 V figure at 10 V, 0.36 at 15 V, in straight lines between, and up to twice as slow by 3 V.

Pin names are the NXP HEF4000B ones (TI letters its gates A to M instead). Aliases: 4001, 4011, 4071, 4081, 4070, 4030, 4077, 4002, 4012, 4023, 4025, 4069, 4049, 4050, 4093, 40106, CD4011BE, HEF4011B, MC14011, HEF4001B, MC14001, CD4069UB, CD4049UB, CD40106B, quad NAND, quad NOR, hex inverter, Schmitt trigger, CMOS gate.

CD4001, CD4011, CD4071, CD4081, CD4070, CD4030 and CD4077: quad 2-input gates

Four two-input gates in a 14-pin package, all on one pinout:

Chip	Gate	Y is high when	Delay at 5 V
CD4001	NOR	both inputs are low	125 ns
CD4011	NAND	either input is low	125 ns
CD4071	OR	either input is high	125 ns
CD4081	AND	both inputs are high	125 ns
CD4070	XOR	the inputs differ	140 ns
CD4030	XOR (the older one)	the inputs differ	140 ns
CD4077	XNOR	the inputs agree	140 ns

Pin	Name	What it does
1, 2	1A, 1B	Gate 1 inputs.
3	1Y	Gate 1 output.
5, 6	2A, 2B	Gate 2 inputs.
4	2Y	Gate 2 output.
8, 9	3A, 3B	Gate 3 inputs.
10	3Y	Gate 3 output.
12, 13	4A, 4B	Gate 4 inputs.
11	4Y	Gate 4 output.
7	VSS	Ground.
14	VDD	Supply, 3 V to 18 V.

This is not the 7400 pinout. Gates 1 and 3 match it, but gates 2 and 4 have the output first (pins 4 and 11). Two CD4001 or CD4011 gates cross-coupled make a set-reset latch, and the usual CMOS oscillators and one-shots are built from them.

CD4002 and CD4012: dual 4-input gates

Two gates of four inputs each: the CD4002 is NOR (Y high only when all four inputs are low), the CD4012 is NAND (Y low only when all four are high). Delay: 125 ns at 5 V.

Pin	Name	What it does
2 to 5	1A to 1D	Gate 1 inputs.
1	1Y	Gate 1 output.
9 to 12	2A to 2D	Gate 2 inputs.
13	2Y	Gate 2 output.
6, 8	NC6, NC8	Not connected.
7	VSS	Ground.
14	VDD	Supply, 3 V to 18 V.

CD4023 and CD4025: triple 3-input gates

Three gates of three inputs each: the CD4023 is NAND and the CD4025 is NOR. Delay: 125 ns at 5 V. Not the 7410 pinout: gate 1 is split, with 1C on pin 8 and 1Y on pin 9.

Pin	Name	What it does
1, 2, 8	1A, 1B, 1C	Gate 1 inputs.
9	1Y	Gate 1 output.
3, 4, 5	2A, 2B, 2C	Gate 2 inputs.
6	2Y	Gate 2 output.
13, 12, 11	3A, 3B, 3C	Gate 3 inputs.
10	3Y	Gate 3 output.
7	VSS	Ground.
14	VDD	Supply, 3 V to 18 V.

CD4069: hex inverter

The CD4069UB: six inverters on the 74HC04 pinout. Delay: 55 ns at 5 V. The UB means unbuffered (one transistor pair per gate), which is why it is the chip people bias into its linear region as an amplifier or a crystal oscillator. The model is a logic inverter switching at half the supply; that analog use is not modeled.

Pin	Name	What it does
1, 3, 5, 9, 11, 13	1A to 6A	Inputs.
2, 4, 6, 8, 10, 12	1Y to 6Y	Outputs, the inverse of their input.
7	VSS	Ground.
14	VDD	Supply, 3 V to 18 V.

CD4049 and CD4050: hex buffers and level shifters

Six buffers each: the CD4049UB inverts, the CD4050B does not. Their inputs may go above VDD (up to 18 V), which makes them the classic way to bring a 9 V or 12 V signal down to 5 V logic: power the chip from the low supply and feed it the high signal. Delays at 5 V: 46 ns for the CD4049 and 62 ns for the CD4050, each the average of the data sheet's rise and fall figures (60 and 32 ns, 70 and 55 ns). The supply is on pins 1 and 8, not the corners.

Pin	Name	What it does
3, 5, 7, 9, 11, 14	1A to 6A	Inputs. May go above VDD.
2, 4, 6, 10, 12, 15	1Y to 6Y	Outputs.
13, 16	NC13, NC16	Not connected.
8	VSS	Ground.
1	VDD	Supply, 3 V to 18 V.

CD4093 and CD40106: Schmitt-trigger gates

The CD4093 is the CD4011 (quad NAND, same pins) and the CD40106 is the CD4069 (hex inverter, same pins), with hysteresis on every input: the 4000-series 74HC14. Each input reads high once it has climbed past VT+ and low once it has dropped below VT-, and holds between the two, so a slow or bouncing signal gives one clean edge. An input that has not left the gap since power-up reads unknown.

The thresholds are the data sheet typicals, VT+ 2.9 V and VT- 1.9 V at 5 V (5.9 and 3.9 V at 10 V, 8.8 and 5.8 V at 15 V), taken as 0.58 and 0.38 of the supply. Delays at 5 V: 190 ns for the CD4093 and 140 ns for the CD40106.

One resistor from an output back to its own input and one capacitor from that input to VSS make an oscillator. On a CD4093, tie the gate's other input high to run it, or use that input as an on/off control: low stops the oscillator with the output high. It is the classic CMOS oscillator and switch debouncer.

Truth table

A	B	NAND	NOR	AND	OR	XOR	XNOR
0	0	1	1	0	0	0	1
0	1	1	0	0	1	1	0
1	0	1	0	0	1	1	0
1	1	0	0	1	1	0	1

Properties

model: each chip has one choice, its own part number (CD4001B, CD4011B, CD4069UB, CD4049UB, CD4050B, CD40106B and so on).

What the model gets right

Controlling values: a 0 on a NAND or AND input, or a 1 on a NOR or OR input, settles the output whatever the other inputs are doing, so a cross-coupled latch climbs out of its unknown power-up state. The outputs are as weak as a real 4000-series output, and the delays get shorter as the supply rises. The Schmitt gates read their inputs as voltages, so a slowly charging capacitor crosses each threshold exactly once. Delays are inertial: a pulse shorter than the delay never reaches the output.

What it does not model

One delay for every gate and both directions, the same scaling with the supply for every chip, and no dependence on load. The CD4049 and CD4050 really sink several times the current of an ordinary 4000-series output; the model drives like the others. The CD4069UB's linear (analog) use is not modeled. The Schmitt gates sit on the typical thresholds, where a real chip can be anywhere in a much wider range, so a real oscillator's frequency varies from chip to chip by tens of percent. No supply current, which on a real chip rises while an input sits between the rails.

Common mistakes

Wiring a CD4001 or CD4011 as if it were a 7400: gates 2 and 4 are the other way around. Leaving unused inputs floating: a floating CMOS input reads unknown here, and on the bench it picks up noise and can make the chip draw current. Tie every unused input to VDD or VSS. Driving an LED straight from an output and expecting full brightness. Wiring a CD4049 or CD4050 as if its power were on the corners.

See it in action

Browse the example circuits at /templates.