74HC00 quad NAND
Four NAND gates in a DIP-14, with supply pins and a real propagation delay.
- 14 pins
- 1 setting
- In 1 project
The 74HC00 quad NAND in brief
What it is, and every setting the properties panel gives it.
The 74HC00 packages four independent two-input NAND gates in one 14-pin chip, with pin 14 as VCC and pin 7 as GND: real catalog pins that have to be wired before any gate does anything at all. Unpowered, every output sits high-impedance rather than at a defined level, which is the single most common reason a logic circuit built from real chips looks dead on first inspection. Each gate answers with a controlling-value rule: a NAND with a 0 on either input already knows its output is 1 regardless of what the other input is doing, even if that other input is unknown, and only needs both inputs resolved when neither is a controlling value. Every input change reaches the output 9 nanoseconds later, the datasheet’s typical figure, and that delay is inertial, so a pulse narrower than 9 nanoseconds never reaches the output at all.
- Family
- Logic
- Pins
- 14
- model
- 74HC00 (or 74HCT00, 74LS00)
14 pins
Named as the editor names them, so a wire lands where you expect it.
Input8
- 1A
- 1B
- 2A
- 2B
- 3A
- 3B
- 4A
- 4B
Output4
- 1Y
- 2Y
- 3Y
- 4Y
Input or output2
- GND
- VCC
How to wire a 74HC00 NAND gate as a latch
The 74HC00 has four two-input NAND gates: the output is low only when both inputs are high. Cross-couple two of them, each output into the other gate’s second input, and you have an SR latch, the smallest circuit that remembers a bit.
The circuit here does exactly that. A slide switch grounds one input or the other, each held high by a 10 k pull-up, so whichever side the switch is on sets the latch that way, and two LEDs show Q and Q-bar. Pins 14 and 7 are the supply; an unpowered chip does nothing.
Unused gates on a real 74HC00 should have their inputs tied to GND or 5 V: a floating CMOS input wastes current and can oscillate.
What is true about the 74HC00 quad NAND, here
In its help article’s own words: what the simulation gets right, and where it stops.
74HC00: quad 2-input NAND gate
The 7400: four independent NAND gates in one 14-pin DIP, pin 7 GND and pin 14
VCC. An input that is unknown or floating still gives a defined output when it
could not change the answer: a 0 on either input of a NAND forces Y high whatever
the other input is doing. Propagation delay: 9 ns typical, from either input to Y.
See it in: NAND latch.
Not modeled
One typical delay, and nothing around it. Each chip carries a single propagation
delay taken from its datasheet's typical column at VCC = 5 V, CL = 15 pF and
25 °C, and uses it for every path through the package. There is no minimum or maximum,
no spread between the gates in one chip, no rise or fall time, no output slew and no
dependence on supply voltage, load capacitance or temperature, all of which a real
74HC part has, and all of which a datasheet gives ranges for. On the 74HC595 the one
figure is the STCP-to-Qn number used for SHCP and MR to Q7S as well, which
the datasheet lists a nanosecond or two apart.
No setup, hold or pulse-width checks. The 74HC74 and the 74HC595 take a clock edge whenever they see one; nothing here refuses data that changed too close to the edge or a clock pulse that was too narrow, and nothing warns about it. A real part would metastable or simply miss.
No supply current, no output current limit and no bus contention damage. An output driving into another output is resolved as two drivers on one net; nothing gets hot.
Sequential parts power up cleared rather than random, because a toggle divider fed Unknown never escapes it. See how faithfully a part behaves.
From The 74HC logic family, in full.
See the 74HC00 quad NAND in a project
One built-in project uses it. It opens in the editor, already wired.
The rest of the bench
Every one of these is drawn and simulated the same way.
Wire up the 74HC00 quad NAND
Open the editor and push it into the breadboard. It is free, and it runs on your own machine.