74HC registers and latches
74HC173, 74HC174, 74HC175, 74HC273, 74HC374, 74HC574 (registers) and 74HC373, 74HC573 (latches): chips that remember four, six or eight bits at once.
The difference between the two kinds is the whole point of choosing one:
- A register (D flip-flops) takes its inputs on the rising edge of its clock
CPand holds them until the next rising edge, whatever the inputs do in between. - A latch is transparent while its latch enable
LEis high (the outputs follow the inputs) and holds what the inputs were at the momentLEfalls.
Aliases: 74173, 74174, 74175, 74273, 74373, 74374, 74573, 74574, SN74HC273, SN74HC373, SN74HC574, 74LS273, 74LS373, 74LS374, 74HCT573, octal latch, octal D flip-flop, D register, data register, bus register.
74HC173: 4-bit D register with tri-state outputs
Four D flip-flops on one rising-edge clock, with a load enable, a reset and output
enables. The data loads only while both data enables E1 and E2 are low; with
either high the clock edge leaves the register as it is. MR (active high)
clears the register at once, without the clock. Both output enables OE1 and OE2
have to be low for Q0 to Q3 to drive; with either high the outputs are off and
the register still clocks. Delays: 17 ns from the clock, 12 ns from MR and 12 ns
from an output enable, the CD74HC173 typicals at 5 V and 15 pF.
| Pin | Name | What it does |
|---|---|---|
| 14, 13, 12, 11 | D0 to D3 |
Data inputs. |
| 3 to 6 | Q0 to Q3 |
Tri-state outputs. |
| 7 | CP |
Clock, rising edge. |
| 9, 10 | E1, E2 |
Data enables, active low. Both low to load. |
| 1, 2 | OE1, OE2 |
Output enables, active low. Both low to drive. |
| 15 | MR |
Master reset, active high. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
74HC174: hex D flip-flop with reset
Six D flip-flops on one rising-edge clock CP, Q outputs only, and an active-low
reset MR that clears all six at once. Delays: 17 ns from the clock or MR, the
SN74HC174 typicals at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 3, 4, 6, 11, 13, 14 | D0 to D5 |
Data inputs. |
| 2, 5, 7, 10, 12, 15 | Q0 to Q5 |
Outputs. |
| 9 | CP |
Clock, rising edge. |
| 1 | MR |
Master reset, active low. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
74HC175: quad D flip-flop with reset
Four D flip-flops on one rising-edge clock CP, each with Q and QN outputs, and
an active-low reset MR that clears all four at once. Delays: 16 ns from the clock
and 15 ns from MR, the SN74HC175 typicals at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 4, 5, 12, 13 | D0 to D3 |
Data inputs. |
| 2, 7, 10, 15 | Q0 to Q3 |
Outputs. |
| 3, 6, 11, 14 | Q0N to Q3N |
Complement outputs. |
| 9 | CP |
Clock, rising edge. |
| 1 | MR |
Master reset, active low. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
74HC273: octal D flip-flop with reset
Eight D flip-flops on one rising-edge clock CP, with an active-low reset MR that
clears all eight at once. There is no output enable: the register drives Q0 to Q7
all the time, which is why 8-bit computer builds use it for registers that feed LEDs.
Delays: 15 ns from the clock or MR, the SN74HC273 typicals at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 3, 4, 7, 8, 13, 14, 17, 18 | D0 to D7 |
Data inputs. |
| 2, 5, 6, 9, 12, 15, 16, 19 | Q0 to Q7 |
Outputs. |
| 11 | CP |
Clock, rising edge. |
| 1 | MR |
Master reset, active low. |
| 10 | GND |
Ground. |
| 20 | VCC |
Supply. |
74HC374: octal D flip-flop with tri-state outputs
Eight D flip-flops on one rising-edge clock CP, with an active-low output enable
OE: the register on a shared bus. With OE high the outputs are off and the
register still clocks. Same pinout as the 74HC273, with OE where the 273 has MR.
Delays: 17 ns from the clock and 16 ns from OE, the SN74HC374 typicals at 4.5 V and
50 pF.
| Pin | Name | What it does |
|---|---|---|
| 3, 4, 7, 8, 13, 14, 17, 18 | D0 to D7 |
Data inputs. |
| 2, 5, 6, 9, 12, 15, 16, 19 | Q0 to Q7 |
Tri-state outputs. |
| 11 | CP |
Clock, rising edge. |
| 1 | OE |
Output enable, active low. |
| 10 | GND |
Ground. |
| 20 | VCC |
Supply. |
74HC373: octal transparent latch with tri-state outputs
Eight D latches with a shared latch enable LE, on the 74HC374's pinout (LE where
the 374 has CP). While LE is high, Q follows D; when LE falls, it holds.
OE (active low) turns the outputs on; with OE high they are off and the latch
still works. Delays: 15 ns from D and 17 ns from OE, the SN74HC373 typicals at
4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 3, 4, 7, 8, 13, 14, 17, 18 | D0 to D7 |
Data inputs. |
| 2, 5, 6, 9, 12, 15, 16, 19 | Q0 to Q7 |
Tri-state outputs. |
| 11 | LE |
Latch enable. High: transparent. Falling: holds. |
| 1 | OE |
Output enable, active low. |
| 10 | GND |
Ground. |
| 20 | VCC |
Supply. |
74HC573 and 74HC574: flow-through pinout
The 74HC573 is the 74HC373's latch and the 74HC574 the 74HC374's register, with the
inputs down one side of the package and the outputs down the other, which is far
easier to wire. The behavior is the same. Delays: on the 74HC573, 26 ns from D and
24 ns from OE (SN74HC573A typicals at 4.5 V and 50 pF); on the 74HC574, 28 ns from
the clock and 26 ns from OE (SN74HC574).
| Pin | Name | What it does |
|---|---|---|
| 2 to 9 | D0 to D7 |
Data inputs. |
| 19 to 12 | Q0 to Q7 |
Tri-state outputs. Q0 is pin 19, opposite D0. |
| 11 | LE (573) or CP (574) |
Latch enable, or clock on the rising edge. |
| 1 | OE |
Output enable, active low. |
| 10 | GND |
Ground. |
| 20 | VCC |
Supply. |
Truth table
A register (74HC173, 174, 175, 273, 374, 574):
MR |
CP |
Q |
|---|---|---|
| active | x | 0 |
| inactive | rising | D |
| inactive | anything else | Holds |
A latch (74HC373, 573):
LE |
Q |
|---|---|
| 1 | Follows D |
| falling | Holds what D was |
| 0 | Holds |
On every chip with an output enable, the enable only switches the outputs off; the register or latch underneath carries on, and its contents reappear when the outputs come back on.
Properties
model: each chip offers its 74HC, 74HCT and 74LS versions (for example 74HC574,
74HCT574, 74LS574). The 74HC version runs from 2 V to 6 V and switches at half the
supply. The 74HCT version needs 4.5 V to 5.5 V and switches at 1.4 V (TTL levels).
The 74LS version needs 4.75 V to 5.25 V, switches at 1.4 V, drives an output high only
to about 3.4 V, and reads a floating input as high. Pins, logic and delays are the
same in every version: the delays are the 74HC figures.
What the model gets right
Resets are asynchronous and beat the clock. The data taken on a clock edge (or when
LE falls) is the data as it was just before it, so one register can feed the next
on the same clock. An output that is off really lets go of the bus. The chip's own
power-up is not read as a clock edge. Delays are each data sheet's typicals, per
path: clock (or data, for a latch), reset and output enable.
What it does not model
Everything powers up cleared, where a real chip comes up holding whatever its
flip-flops fell into. No setup, hold or pulse-width checks. On the latches, the delay
from LE is taken to be the delay from D (the data sheets give 18 ns from LE on
the 74HC373 and 27 ns on the 74HC573). One figure for each path in both directions,
with no dependence on load. No damage from two enabled outputs fighting over a bus.
Common mistakes
Using a latch where you need a register: while LE is high, every change on the
inputs goes straight through. Getting the reset sense wrong: MR is active high
on the 74HC173 and active low on the 174, 175 and 273. Leaving OE floating (tie it
to GND to keep the outputs on), and forgetting the 74HC173's two data enables,
which have to be low for it to load anything.
See it in action
Browse the example circuits at /templates.