CD4060 oscillator and 14-stage counter

A clock and a divider in one chip: an RC oscillator and fourteen flip-flops, for delays of seconds or minutes.

Two resistors and a capacitor make the oscillator on three of its pins, and the flip-flops divide it down, so a few hertz to a few hundred kilohertz in gives seconds or minutes out.

It is the chip behind slow blinkers, kitchen timers and "turn off after ten minutes" circuits, where a 555 would need an impractically large capacitor. The same catalog part is also the 74HC4060 (set model). Aliases: 4060, CD4060BE, HEF4060B, MC14060, 74HC4060, CD74HC4060, 14-stage ripple counter, oscillator divider, binary counter with oscillator, long timer.

Pins

Pin	Name	What it does
11	`PI`	Oscillator input (`φI` on the data sheet). The counter advances on each falling edge here.
10	`PON`	Oscillator output, the complement of `PI` (`φO` with a bar).
9	`PO`	Oscillator output, the complement of `PON` (`φO`).
12	`MR`	Reset, active high. Clears every stage and stops the oscillator.
7, 5, 4, 6, 14, 13, 15	`Q4` to `Q10`	Stage outputs: `Qn` is the oscillator divided by 2 to the n.
1, 2, 3	`Q12`, `Q13`, `Q14`	Stage outputs. There is no `Q11` pin, and no `Q1` to `Q3`.
8	`VSS`	Ground.
16	`VDD`	Supply: 3 V to 18 V for the CD4060B, 2 V to 6 V for the 74HC4060.

The oscillator

The data sheet's circuit: RS from PI to a node, RX from PON to that node, and the capacitor CX from the node to PO. The period is about 2.2 RX CX, the data sheet's figure. RS (2 to 10 times RX) keeps the input's own current out of the timing.

For example, RX = 10 k and CX = 100 nF give a period of 2.2 ms (about 455 Hz). Q4 then toggles at a sixteenth of that and Q14 at 1/16384 of it, a period of about 36 seconds.

To use an external clock instead, drive PI and leave PO and PON open.

Truth table

`MR`	`PI`	What happens
1	x	Every stage cleared, oscillator stopped (`PON` low, `PO` high)
0	falling	Count moves on by one
0	anything else	Count holds

Properties

model, which chip it is:

CD4060B (the default): 3 V to 18 V, outputs of a few hundred ohms (2000 / VDD ohms, about 400 ohms at 5 V), and slow: 370 ns from PI to Q4 at 5 V, 100 ns more for each stage after that, and 180 ns from MR (CD4060B typicals at 50 pF). The delays shrink as the supply rises.
74HC4060: the same pins, 2 V to 6 V, strong 74HC outputs, and fast: 25 ns from PI to Q4, 6 ns per stage, and 14 ns from MR (CD74HC4060 typicals at 5 V and 15 pF).

What the model gets right

The oscillator really oscillates. The model reads PI as a voltage against half the supply and asks the analog solver to land on each crossing, so the RC network on the three pins runs at the period its parts give, not a period set somewhere else.

It is a ripple counter. Each stage is one stage delay later than the one before, so the high outputs settle well after Q4, as on the real chip. MR clears it at once and stops the oscillator.

What it does not model

The real oscillator input is a Schmitt trigger; here it switches at half the supply with no hysteresis, and the input protection diodes that RS isolates are not modeled, so leaving RS out changes nothing here where it would on the bench. The oscillator inverters' own delay is taken as the counter's first-stage delay. A real oscillator starts from noise; this one starts as if PI were low. The counter powers up cleared. No minimum pulse widths.

Common mistakes

Leaving MR floating: tie it to VSS, or the count goes unknown. Looking for Q1 to Q3 or Q11: they are not brought out. Putting the capacitor on the wrong pin: it goes from the timing node to PO (pin 9), with RX to PON (pin 10) and RS to PI (pin 11).

See it in action

Browse the example circuits at /templates.