More shift registers
74HC164, 74HC166, 74HC597 and TPIC6B595: the shift registers beside the 74HC595 and the 74HC165.
A shift register moves its bits along one place on every clock edge. Serial in, parallel out (the 164 and the TPIC6B595) turns three microcontroller pins into eight outputs; parallel in, serial out (the 166 and the 597) turns eight inputs into one pin's worth of bits. Aliases: 74164, 74166, 74597, SN74HC164, CD74HC597, 74LS164, 74HCT164, TPIC6B595N, SIPO, PISO, serial to parallel, parallel to serial, power shift register, relay driver.
74HC164: 8-bit serial-in, parallel-out shift register
On each rising edge of CP, Q0 to Q6 move up one place to Q1 to Q7, and Q0
takes DSA AND DSB, the two serial inputs gated together: tie one high and clock
data into the other, or use the second as a data gate. MR low clears all eight at
once. There is no output latch: the outputs ripple as the bits shift through,
which is what the 74HC595's latch exists to hide. Delays: 23 ns from the clock and
28 ns from MR, the SN74HC164 typicals at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 1, 2 | DSA, DSB |
Serial inputs, ANDed together. |
| 3 to 6 | Q0 to Q3 |
Outputs. |
| 10 to 13 | Q4 to Q7 |
Outputs. Q7 also feeds the next chip's DSA. |
| 8 | CP |
Clock, rising edge. |
| 9 | MR |
Master reset, active low. |
| 7 | GND |
Ground. |
| 14 | VCC |
Supply. |
74HC166: 8-bit parallel-in, serial-out shift register
Reads eight inputs D0 to D7 at once and shifts them out on Q7, one per clock.
Everything happens on the rising clock edge: with PE (parallel enable, active low)
low the edge loads D0 to D7; with PE high it shifts the register up one place
and the first stage takes DS. Unlike the 74HC165, the load waits for the clock.
CE (clock enable, active low) is ORed with CP inside the chip: CE high holds the
register, and either pin rising while the other is low is a clock edge. MR low
clears all eight at once. Delays: 15 ns from the clock and 18 ns from MR, the
SN74HC166 typicals at 4.5 V and 50 pF.
| Pin | Name | What it does |
|---|---|---|
| 2 to 5 | D0 to D3 |
Parallel inputs. |
| 10, 11, 12, 14 | D4 to D7 |
Parallel inputs. |
| 1 | DS |
Serial input, into the first stage. |
| 13 | Q7 |
Serial output, the last stage. |
| 7 | CP |
Clock, rising edge. |
| 6 | CE |
Clock enable, active low. |
| 15 | PE |
Parallel enable, active low: low loads on the next clock edge. |
| 9 | MR |
Master reset, active low. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
74HC597: shift register with input storage register
The 74HC165's parallel-in, serial-out shift register with an 8-bit storage register
in front of it, so eight inputs can be sampled at one instant and shifted out later.
Delays from the CD74HC597 typicals at 5 V and 15 pF: 14 ns from SHCP or MR, 17 ns
from PL, 20 ns from STCP.
| Pin | Name | What it does |
|---|---|---|
| 15, 1 to 7 | D0 to D7 |
Parallel inputs. D0 is pin 15. |
| 12 | STCP |
Storage clock. Rising copies D0 to D7 into the storage register. |
| 13 | PL |
Parallel load, active low. Copies the storage register into the shift register, at once and for as long as it is held. |
| 11 | SHCP |
Shift clock. Rising (with PL high) shifts the register along. |
| 14 | DS |
Serial input, into the first stage. |
| 9 | Q7 |
Serial output, the last stage. |
| 10 | MR |
Clears the shift register (not the storage register), active low. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply. |
Reading it is three steps: pulse STCP to sample the inputs, pulse PL low to load
the sample, then clock SHCP eight times and read Q7 before each edge. MR and
PL low together is invalid on the data sheet; the model takes the reset as the
stronger, as the data sheet draws it.
TPIC6B595: power shift register
A 74HC595 whose eight outputs are power transistors. Each DRAINn sinks current to
ground when its stored bit is 1 and lets go when it is 0, so a relay, a solenoid, a
small motor, a lamp or a string of LEDs on a supply up to 50 V hangs straight off it
(with its own flyback diode where it is a coil). The data sheet rates each drain at
up to 150 mA.
| Pin | Name | What it does |
|---|---|---|
| 3 | SERIN |
Serial input, into the first stage. |
| 13 | SRCK |
Shift clock, rising edge. |
| 12 | RCK |
Storage clock. Rising copies the shift register to the drains. |
| 8 | SRCLR |
Clears the shift register (not the storage register), active low. |
| 9 | G |
Output enable, active low. High turns every drain off. |
| 4 to 7 | DRAIN0 to DRAIN3 |
Open-drain power outputs. |
| 14 to 17 | DRAIN4 to DRAIN7 |
Open-drain power outputs. |
| 18 | SEROUT |
The last stage, a logic output for the next chip's SERIN. |
| 10, 11, 19 | GND, GND2, GND3 |
Ground. Wiring any one of them grounds the chip. |
| 2 | VCC |
Logic supply, 4.5 V to 5.5 V. Not a corner pin. |
| 1, 20 | NC1, NC20 |
Not connected. |
A 1 turns a drain on, so the stored byte 00000001 pulls DRAIN0 low: the
opposite sense of reading a 74HC595's Q0. A load goes from its own supply to the
drain. Each drain is modeled as 4.2 ohms to ground when on (the data sheet's typical
on-resistance at 25 °C), so a load divides against it. As on the 74HC595, the storage
register takes the shift register as it was before the clock edge, so tying RCK to
SRCK leaves the drains one bit behind. The drains switch 150 ns after G (the data
sheet's turn-off figure; turn-on is 90 ns), and the model uses that one delay for
every path, since the data sheet gives none for the clocks.
Properties
model:
- 74HC164, 74HC166 and 74HC597 offer their 74HC, 74HCT and 74LS versions (for example 74HC164, 74HCT164, 74LS164). The 74HC version runs from 2 V to 6 V and switches at half the supply. The 74HCT version needs 4.5 V to 5.5 V and switches at 1.4 V (TTL levels). The 74LS version needs 4.75 V to 5.25 V, switches at 1.4 V, drives an output high only to about 3.4 V, and reads a floating input as high. Pins, logic and delays are the same in every version: the delays are the 74HC figures.
- TPIC6B595 offers only TPIC6B595.
What the model gets right
Each clock edge takes the data as it was just before it, so Q7 of one chip can feed
the serial input of the next on the same clock. Resets are asynchronous. The chip's
own power-up is not read as a clock. A clock edge out of an unknown level makes the
register unknown rather than guessing. The TPIC6B595's drains only pull down, through
a realistic on-resistance.
What it does not model
Everything powers up cleared. No setup, hold or pulse-width checks. On the TPIC6B595: no 150 mA limit, no thermal shutdown and no output clamps, so nothing burns however hard a drain is driven, and its logic inputs are read at half the supply like a 74HC part.
Common mistakes
Leaving MR (or SRCLR) floating: tie it to VCC. On the 74HC164, leaving the
second serial input floating: tie it high, or every 1 shifts in as unknown. On the
74HC166, expecting PE low to load at once: it loads on the next clock edge. On the
TPIC6B595, wiring a load from a drain to ground (it goes from the load's supply to the
drain), leaving G floating (tie it to GND), and forgetting the flyback diode on a
relay or solenoid.
See it in action
Browse the example circuits at /templates.