CD4026 counter and display driver
A decade counter that drives a common-cathode seven-segment display by itself, so each clock edge shows the next digit.
Every rising clock edge counts on by one, 9 rolls over to 0, and the segment outputs show the count.
One chip, one display, one clock, and you have a counter you can read, with no decoder in between. Chain a second one off the carry and it counts to 99. Aliases: 4026, CD4026BE, CD4026B, counter display driver, decade counter, seven segment counter.
It is a 4000-series CMOS part: its supply pins are VDD and VSS, it runs from 3 V
to 18 V, and its outputs are weak (see below).
Pins
| Pin | Name | What it does |
|---|---|---|
| 1 | CLK |
Clock. The count moves on a rising edge. |
| 2 | INH |
Clock inhibit. Low lets the clock count; high freezes the count. |
| 15 | RST |
Reset. High sends the count to 0 at once and holds it there. |
| 10, 12, 13, 9, 11, 6, 7 | a to g |
Segment outputs, high to light a segment. |
| 3 | DEI |
Display enable in. Low turns every segment output off. |
| 4 | DEO |
Display enable out: follows DEI, for the next digit. |
| 5 | CO |
Carry out. High for counts 0 to 4, low for 5 to 9. |
| 14 | UCS |
Ungated segment c: segment c without the display enable. |
| 8 | VSS |
Ground. |
| 16 | VDD |
Supply, 3 V to 18 V. |
Truth table
RST |
INH |
CLK |
What happens |
|---|---|---|---|
| 1 | x | x | Count goes to 0 |
| 0 | 0 | rising | Count moves on by one (9 goes to 0) |
| 0 | falling | 1 | Count moves on by one |
| 0 | 1 | x | Count holds |
Inside the chip the clock and the inhibit are one gate, CLK AND NOT INH, which is
why a falling INH while CLK is high also counts.
| Count | Segments lit | CO |
|---|---|---|
| 0 | a b c d e f | 1 |
| 1 | b c | 1 |
| 2 | a b d e g | 1 |
| 3 | a b c d g | 1 |
| 4 | b c f g | 1 |
| 5 | a c d f g | 0 |
| 6 | a c d e f g | 0 |
| 7 | a b c | 0 |
| 8 | a b c d e f g | 0 |
| 9 | a b c d f g | 0 |
Unlike the CD4511's, the 4026's 6 and 9 have their tails. CO rises as the count rolls
from 9 to 0, so it is a square wave at a tenth of the clock: wire it to the next
CD4026's CLK to make the tens digit. UCS is low only at the count of 2, whatever
DEI is doing, which is what lets the chip count to 2 (for a clock divider) while the
display is off.
Properties
model: CD4026B, the only choice.
What the model gets right
The outputs are weak. A 4000-series output is a few hundred ohms: the model uses
2000 / VDD ohms, about 400 ohms at 5 V, so a segment LED gets a few milliamps at 5 V
and glows rather than blazes, as on a real breadboard.
It is slow, and faster on a higher supply. From the CD4026B data sheet's typical column at 5 V and 50 pF: 350 ns from the clock to the segments, 250 ns to the carry, and 300 ns from the reset. The delays shrink as the supply rises.
A clock edge out of an unknown level makes the count unknown, and the chip's own power-up is not read as a clock edge.
What it does not model
The five-stage Johnson counter inside a real 4026 is modeled as the count 0 to 9 it
decodes to, which is all its pins ever show (the real counter cannot reach an invalid
state either). CO is taken to be high for 0 to 4, as on the CD4017,
which has the same counter. It powers up at 0. No minimum pulse widths: a clock pulse
of any length counts. No current limit on the segment outputs.
Common mistakes
Leaving RST, INH or DEI unconnected: a floating CMOS input reads unknown, so the
count or the display goes unknown. Tie RST and INH to VSS and DEI to VDD. Using
a common-anode display, which needs the segments pulled low and will not light from
this chip. Clocking it from a bare push button, which bounces and counts several times
per press.
See it in action
Browse the example circuits at /templates.