CD4020, CD4040 and CD4024 ripple counters

Long binary counters: a chain of flip-flops, each one toggled when the one before it falls, so each output is the clock divided by another factor of two.

They are frequency dividers first and counters second: feed one a fast clock and take a slow one off a high output. The CD4020 has 14 stages (divide by up to 16384), the CD4040 12 (up to 4096) and the CD4024 7 (up to 128). For one with its own oscillator built in, see the CD4060. Aliases: 4020, 4040, 4024, CD4020BE, CD4040BE, CD4024BE, HEF4040B, MC14040, 74HC4020, 74HC4040, 74HC4024, CD74HC4040, binary ripple counter, frequency divider, divide by 2.

All three count on the falling edge of CP, and Q1 is the clock divided by 2, Q2 by 4, and so on: Qn divides by 2 to the n. MR (reset, active high) clears every stage at once and holds them clear for as long as it is high.

CD4020: 14-stage counter

Q1 and Q4 to Q14 are brought out; Q2 and Q3 are not.

Pin	Name	What it does
10	CP	Clock. Counts on the falling edge.
11	MR	Reset, active high.
9	Q1	Clock divided by 2.
7, 5, 4, 6	Q4 to Q7	Clock divided by 16 to 128.
13, 12, 14, 15	Q8 to Q11	Clock divided by 256 to 2048.
1, 2, 3	Q12, Q13, Q14	Clock divided by 4096, 8192 and 16384.
8	VSS	Ground.
16	VDD	Supply.

CD4040: 12-stage counter

All twelve stages are brought out, so it is a full 12-bit binary counter.

Pin	Name	What it does
10	CP	Clock. Counts on the falling edge.
11	MR	Reset, active high.
9, 7, 6	Q1, Q2, Q3	Clock divided by 2, 4 and 8.
5, 3, 2, 4	Q4 to Q7	Clock divided by 16 to 128.
13, 12, 14, 15	Q8 to Q11	Clock divided by 256 to 2048.
1	Q12	Clock divided by 4096.
8	VSS	Ground.
16	VDD	Supply.

CD4024: 7-stage counter

A 14-pin package with all seven stages brought out.

Pin	Name	What it does
1	CP	Clock. Counts on the falling edge.
2	MR	Reset, active high.
12, 11, 9	Q1, Q2, Q3	Clock divided by 2, 4 and 8.
6, 5, 4, 3	Q4 to Q7	Clock divided by 16 to 128.
8, 10, 13	NC8, NC10, NC13	Not connected.
7	VSS	Ground.
14	VDD	Supply.

Truth table

MR	CP	What happens
1	x	Every stage cleared
0	falling	Count moves on by one
0	anything else	Count holds

To make a counter that resets at some count other than a power of two, AND together the outputs that are high at that count and feed the result to MR: the counter clears the moment it gets there.

Properties

model, which chip it is. Each part offers its CD4000B and 74HC version, on the same pins (both use the supply names VDD and VSS):

• CD4020B, CD4040B, CD4024B (the default): 3 V to 18 V, outputs of a few hundred ohms (2000 / VDD ohms, about 400 ohms at 5 V), and slow. From the data sheet typicals at 5 V and 50 pF: about 180 ns from the clock to Q1, 100 ns more for each stage after it, and 140 ns from MR. So the last output settles microseconds after the clock edge. The delays shrink as the supply rises.
• 74HC4020, 74HC4040, 74HC4024: 2 V to 6 V, strong 74HC outputs, and a few nanoseconds a stage. From the CD74HC40xx typicals at 5 V and 15 pF: 11 ns from the clock to Q1, 6 ns per stage (4 ns on the 74HC4040), and 14 ns from MR.

What the model gets right

It ripples. Each output changes one stage delay after the one before it, so for a moment after a clock edge the outputs show counts that are not the real one, exactly the glitches that make a ripple counter a poor choice for driving a decoder directly. On the CD4000B parts, with 100 ns a stage, that window is long enough to see on a logic analyzer. MR is asynchronous, and a clock edge out of an unknown level makes the count unknown.

What it does not model

It powers up cleared, where a real counter comes up holding anything. No minimum clock pulse width or maximum clock frequency: a clock of any speed counts. One delay per stage, with no dependence on load.

Common mistakes

Leaving MR floating: tie it to VSS, or the count goes unknown. Expecting the count to move on the rising edge. Looking for Q2 and Q3 on a CD4020: they are not brought out. Using a reset-on-count trick with a decoder that sees the ripple glitches and resets too early.

See it in action

Browse the example circuits at /templates.