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74-series counters

74LS90, 74LS93, 74HC390, 74HC393, 74HC190, 74HC191 and 74HC192: counters that count in tens or in sixteens, up only or up and down.

They come in two kinds:

  • Ripple counters (74LS90, 74LS93, 74HC390, 74HC393) count on the falling edge of their clock, and each stage clocks the next, so the outputs settle one after another. They are cheap, simple and the standard frequency dividers.
  • Synchronous up/down counters (74HC190, 74HC191, 74HC192) count on the rising edge, every output together, can count down as well as up, and can be loaded with any starting number.

For the 4-bit two-clock binary counter see the 74HC193, and for the 74HC161 see its own page. Aliases: 7490, 7493, 74390, 74393, 74190, 74191, 74192, SN74LS90, SN74LS93, CD74HC390, SN74HC393, CD74HC190, CD74HC192, decade counter, BCD counter, binary counter, divide by 10, frequency divider, up/down counter.

74LS90: decade counter

A divide-by-2 counter (CKA in, QA out) and a divide-by-5 counter (CKB in, QB QC QD out) in one package, both counting on the falling edge. Wire QA to CKB and clock CKA, and QD QC QB QA count 0 to 9 in BCD. Wire QD to CKA and clock CKB instead, and QA is a square wave at a tenth of the clock. The supply is on pins 5 and 10, not the corners.

Pin Name What it does
14 CKA Clock for the divide-by-2, falling edge.
1 CKB Clock for the divide-by-5, falling edge.
12 QA Divide-by-2 output, the 1s bit of the BCD count.
9, 8, 11 QB, QC, QD Divide-by-5 outputs.
2, 3 R01, R02 Reset to 0: both high clears the count.
6, 7 R91, R92 Set to 9: both high sets QA and QD, and wins over R01 and R02.
4, 13 NC4, NC13 Not connected.
10 GND Ground.
5 VCC Supply, 5 V.

It was made in TTL only (the 74HC390 is the CMOS decade counter), so it reads TTL input levels, switching at 1.4 V, its output high sits near 3.4 V, and a floating input reads high: leave the reset pins open and the chip sits at 9 and never counts. Tie all four to GND. Delays, the SN74LS90 typicals at 5 V and 15 pF: 12 ns from CKA to QA, 14 ns from CKB to QB, 23 ns to QC and QD, and 26 ns from a reset. Wired QA to CKB, the carry goes through the outside wire, so QD arrives after both.

74LS93: 4-bit binary counter

The 74LS90's binary twin: a divide-by-2 (CKA to QA) and a divide-by-8 (CKB to QB QC QD), both on the falling edge. Wire QA to CKB and clock CKA, and QD QC QB QA count 0 to 15. R01 and R02 both high clear it. TTL only, with the same behavior as the 74LS90 (the 74HC393 is the CMOS one), and the same supply on pins 5 and 10. Delays, the SN74LS93 typicals at 5 V and 15 pF: 12 ns from CKA to QA, 14 ns from CKB to QB, 23 ns to QC, 34 ns to QD, and 26 ns from a reset.

Pin Name What it does
14 CKA Clock for the divide-by-2, falling edge.
1 CKB Clock for the divide-by-8, falling edge.
12 QA Divide-by-2 output, the 1s bit.
9, 8, 11 QB, QC, QD Divide-by-8 outputs.
2, 3 R01, R02 Reset: both high clears the count.
4, 6, 7, 13 NC4, NC6, NC7, NC13 Not connected.
10 GND Ground.
5 VCC Supply, 5 V.

74HC390: dual decade ripple counter

Two 7490-style counters, each a divide-by-2 (nCP0 in, nQ0 out) and a divide-by-5 (nCP1 in, nQ1 to nQ3 out), counting on the falling edge. Wire nQ0 to nCP1 and clock nCP0 for a BCD count; wire nQ3 to nCP0 and clock nCP1 for a divide-by-10 square wave on nQ0. nMR (active high) clears that counter at once. Two counters in one package divide by 100. Delays, the CD74HC390 typicals at 5 V and 15 pF: 14 ns from CP0 to Q0, 15 ns from CP1 to Q1 to Q3, and 16 ns from MR.

Pin Name What it does
1 1CP0 Counter 1 divide-by-2 clock, falling edge.
4 1CP1 Counter 1 divide-by-5 clock, falling edge.
3 1Q0 Counter 1 divide-by-2 output.
5, 6, 7 1Q1 to 1Q3 Counter 1 divide-by-5 outputs.
2 1MR Counter 1 reset, active high.
15 2CP0 Counter 2 divide-by-2 clock, falling edge.
12 2CP1 Counter 2 divide-by-5 clock, falling edge.
13 2Q0 Counter 2 divide-by-2 output.
11, 10, 9 2Q1 to 2Q3 Counter 2 divide-by-5 outputs.
14 2MR Counter 2 reset, active high.
8 GND Ground.
16 VCC Supply.

74HC393: dual 4-bit binary ripple counter

Two 4-bit binary counters, each counting on the falling edge of its clock nCP, with an active-high clear nMR. Inside, each stage clocks the next, so the outputs settle one after another, Q3 last. Wire 1Q3 to 2CP for an 8-bit counter. Delays, the SN74HC393 typicals at 4.5 V and 50 pF: 15 ns from the clock to Q0, then about 6 ns more per stage (Q3 at 32 ns), and 17 ns from MR.

Pin Name What it does
1 1CP Counter 1 clock, falling edge.
3 to 6 1Q0 to 1Q3 Counter 1 outputs, 1Q0 the 1s bit.
2 1MR Counter 1 reset, active high.
13 2CP Counter 2 clock, falling edge.
11 to 8 2Q0 to 2Q3 Counter 2 outputs, 2Q0 the 1s bit.
12 2MR Counter 2 reset, active high.
7 GND Ground.
14 VCC Supply.

74HC190 and 74HC191: synchronous up/down counters

One clock, a direction pin, an enable, a load and two carry outputs. The 74HC190 counts 0 to 9 in BCD and the 74HC191 counts 0 to 15 in binary; otherwise they are the same chip on the same pins. There is no reset pin. Delays, the CD74HC190/191 typicals at 5 V and 15 pF: 14 ns from the clock and 16 ns from PL to the count, 18 ns from the clock to TC and 10 ns to RC.

Pin Name What it does
14 CP Clock, rising edge.
5 UD Direction (U/D on the data sheet). Low counts up, high counts down.
4 CE Count enable, active low.
11 PL Parallel load, active low. Low loads D0 to D3 at once, without the clock.
15, 1, 10, 9 D0 to D3 The number PL loads.
3, 2, 6, 7 Q0 to Q3 The count, Q0 the 1s bit.
12 TC Terminal count (MAX/MIN): high at the end of the count in the direction set.
13 RC Ripple clock, active low: low for the low half of the clock while TC is high and the counter is enabled.
8 GND Ground.
16 VCC Supply.
PL CE UD CP What happens
0 x x x Load D0 to D3
1 1 x x Hold
1 0 0 rising Count up (9 or 15 goes to 0)
1 0 1 rising Count down (0 goes to 9 or 15)

TC is high at 9 (190) or 15 (191) counting up, and at 0 counting down. To cascade, wire RC to the next chip's CE (synchronous, both chips on one clock) or to its CP (ripple).

74HC192: synchronous BCD up/down counter with two clocks

The 74HC193's two-clock up/down counter, counting 0 to 9 in BCD, on the same pins. A rising edge on CPU counts up and one on CPD counts down, and the clock you are not using has to sit high. MR (active high) clears the count at once and overrides everything; PL low loads D0 to D3 at once. TCU (carry, active low) goes low while the count is 9 and CPU is low; TCD (borrow) while the count is 0 and CPD is low. Wire them to the next chip's CPU and CPD to count past 9. Delays, the CD74HC192 typicals at 5 V and 15 pF: 18 ns from a clock or PL to the count, 17 ns from MR, 10 ns from a clock to TCU or TCD.

Pin Name What it does
5 CPU Count-up clock.
4 CPD Count-down clock.
3, 2, 6, 7 Q0 to Q3 The count, Q0 the 1s bit.
15, 1, 10, 9 D0 to D3 The number PL loads.
11 PL Parallel load, active low.
14 MR Master reset, active high.
12 TCU Carry, active low.
13 TCD Borrow, active low.
8 GND Ground.
16 VCC Supply.

As on the 74HC193, the two clocks meet in an AND gate inside the chip and the counter moves on its rising edge, so a pulse on one clock while the other is low counts nothing.

Properties

model:

  • 74HC390, 74HC393, 74HC190, 74HC191 and 74HC192 offer their 74HC, 74HCT and 74LS versions (for example 74HC390, 74HCT390, 74LS390). The 74HC version runs from 2 V to 6 V and switches at half the supply. The 74HCT version needs 4.5 V to 5.5 V and switches at 1.4 V (TTL levels). The 74LS version needs 4.75 V to 5.25 V, switches at 1.4 V, drives an output high only to about 3.4 V, and reads a floating input as high. Pins, logic and delays are the same in every version: the delays are the 74HC figures.
  • 74LS90 offers only 74LS90, and 74LS93 only 74LS93.

What the model gets right

The ripple counters' outputs settle in turn, each with its own data sheet delay, so a logic analyzer shows the short wrong counts a ripple counter really passes through on its way. The 74HC190, 191 and 192 carry outputs depend on the clock as well as the count, as the data sheets draw them, so cascading works. Loads and resets are asynchronous. A clock edge out of an unknown level makes the count unknown. The chip's own power-up is not read as a clock.

What it does not model

Every counter powers up at 0, where a real one comes up in whatever state it falls into (the 74HC190 and 74HC191 have no reset pin at all to fix that). No setup, hold or pulse-width checks. The six codes past 9 on the BCD counters (74HC190, 74HC192) are not part of the count: loaded with one, the next count up goes to 0 and the next count down to 9, where a real chip takes one or two counts to get back by its own path.

Common mistakes

Leaving the reset pins floating. On the 74LS90 and 74LS93 they read high, so the counter is held at 0 (or 9) and never counts; on the 74HC parts a floating MR makes the count unknown. Tie them to GND. Expecting a ripple counter to move on the rising edge: they count on the falling edge. Wiring a 74LS90 or 74LS93 as if its power were on the corners. On the 74HC192, tying the unused clock low.

See it in action

Browse the example circuits at /templates.