The 74HC86 quad XOR in brief
What it is, and every setting the properties panel gives it.
The 74HC86 packages four independent two-input XOR gates in one 14-pin chip, wired the same pin layout as the 74HC00: pin 14 is VCC, pin 7 is GND, and both have to be wired before any gate does anything. An XOR has no controlling value the way an AND or OR gate does, since either input alone can flip the answer, so an unknown on either input gives an unknown output regardless of the other input’s level. That makes it the odd one out among the logic families Mokxi models, and it is also what makes an XOR the natural core of a binary adder’s sum bit, or of a simple parity check across several inputs. The same 9 nanosecond typical propagation delay applies here, inertially, so a pulse narrower than that time never reaches the output. Wired next to a 74HC00, as it is on the logic gate simulator page, the two chips answer the same two inputs completely differently, which is the whole point of showing them side by side.
- Family
- Logic
- Pins
- 14
- model
- 74HC86 (or 74HCT86, 74LS86)
14 pins
Named as the editor names them, so a wire lands where you expect it.
Input8
- 1A
- 1B
- 2A
- 2B
- 3A
- 3B
- 4A
- 4B
Output4
- 1Y
- 2Y
- 3Y
- 4Y
Input or output2
- GND
- VCC
How to use a 74HC86 XOR gate in a full adder
The 74HC86 has four two-input XOR gates: the output is high when exactly one input is high. That is binary addition without the carry, which makes the XOR the heart of every adder: sum = A xor B xor Cin.
The circuit here is a one-bit full adder from three chips. Two XOR gates of the 74HC86 make the sum, two AND gates of a 74HC08 and one OR gate of a 74HC32 make the carry, and three slide switches set A, B and Cin. Flip them and two LEDs show the sum and the carry.
Chain four full adders, each carry into the next one’s Cin, and you have a four-bit adder, which is what the 74HC283 does in one package.
What is true about the 74HC86 quad XOR, here
In its help article’s own words: what the simulation gets right, and where it stops.
74HC86: quad 2-input XOR gate
The 7486, same package, four exclusive-OR gates: the adder and parity building block, and the cheapest way to make a controllable inverter. An XOR has no controlling value, so any unknown input gives an unknown output. It sits one gate deeper inside the package than a NAND, so it is slower: propagation delay 12 ns typical. See it in: Full adder.
Not modeled
One typical delay, and nothing around it. Each chip carries a single propagation
delay taken from its datasheet's typical column at VCC = 5 V, CL = 15 pF and
25 °C, and uses it for every path through the package. There is no minimum or maximum,
no spread between the gates in one chip, no rise or fall time, no output slew and no
dependence on supply voltage, load capacitance or temperature, all of which a real
74HC part has, and all of which a datasheet gives ranges for. On the 74HC595 the one
figure is the STCP-to-Qn number used for SHCP and MR to Q7S as well, which
the datasheet lists a nanosecond or two apart.
No setup, hold or pulse-width checks. The 74HC74 and the 74HC595 take a clock edge whenever they see one; nothing here refuses data that changed too close to the edge or a clock pulse that was too narrow, and nothing warns about it. A real part would metastable or simply miss.
No supply current, no output current limit and no bus contention damage. An output driving into another output is resolved as two drivers on one net; nothing gets hot.
Sequential parts power up cleared rather than random, because a toggle divider fed Unknown never escapes it. See how faithfully a part behaves.
From The 74HC logic family, in full.
See the 74HC86 quad XOR in a project
One built-in project uses it. It opens in the editor, already wired.
Where it turns up in a lesson
3 lessons place it in their own circuits.
The rest of the bench
Every one of these is drawn and simulated the same way.
Wire up the 74HC86 quad XOR
Open the editor and push it into the breadboard. It is free, and it runs on your own machine.