74HC161 synchronous counter
A 4-bit binary counter in which every output changes on the same clock edge.
Where a ripple counter (two 74HC74s) lets the carry walk from stage to stage, the 161 clocks all four flip-flops together, so you can read it at any moment without catching a half-counted number. Aliases: 74161, SN74HC161, CD74HC161, synchronous binary counter, presettable counter.
Pins
| Pin | Name | What it does |
|---|---|---|
| 2 | CP |
Clock. Everything that happens, happens on a rising edge. |
| 14, 13, 12, 11 | Q0 to Q3 |
The count, Q0 the 1s bit. |
| 3 to 6 | D0 to D3 |
The number a load puts in. |
| 9 | PE |
Parallel enable (load), active low. Low: the next clock loads D0 to D3. |
| 7 | CEP |
Count enable. |
| 10 | CET |
Count enable that also gates TC. |
| 15 | TC |
Terminal count: high when the count is 15 and CET is high. |
| 1 | MR |
Master reset, active low. Low clears the count at once. |
| 8 | GND |
Ground. |
| 16 | VCC |
Supply, 2 V to 6 V. |
Truth table
MR |
PE |
CEP |
CET |
CP |
What happens |
|---|---|---|---|---|---|
| 0 | x | x | x | x | Clear to 0 (no clock needed) |
| 1 | 0 | x | x | rising | Load D0 to D3 |
| 1 | 1 | 1 | 1 | rising | Count up (15 goes to 0) |
| 1 | 1 | 0 | x | x | Hold |
| 1 | 1 | x | 0 | x | Hold |
Two 161s make an 8-bit counter: share the clock, and wire the first chip's TC to the
second chip's CEP and CET.
Properties
None.
What the model gets right
The reset is asynchronous and the load is synchronous, which is the one difference
between the 161 and its sibling the 163 (whose reset waits for the clock too). All four
outputs move one delay after the clock edge, together. Delays are the CD74HC161
typicals at 5 V and 15 pF: 15 ns from the clock to the count and to TC, 18 ns from
MR, and 9 ns from CET to TC.
What it does not model
No setup or hold times against the clock, and one delay per path. It powers up at 0. An enable that cannot be read (floating) on a clock edge makes the count unknown.
Common mistakes
Expecting PE low to load at once: it waits for the next clock. Leaving CEP or CET
floating, which stops the count being known; tie both to VCC to count.
See it in action
Decoder chaser clocks a 161 from a 74HC14 oscillator and decodes its count with a 74HC138. Open it at /templates.