Part

74HC74 dual flip-flop

Two D flip-flops with preset and clear. Divide a clock with one.

See every part
  • 14 pins
  • In 1 project
  • In 3 lessons
Drawn live by the editor's own code, at the size you see it.
At a glance

The 74HC74 dual flip-flop in brief

What it is, and where it sits on the bench.

The 74HC74 packages two independent D-type flip-flops, each with a data input, a clock, and an active-low set and reset that both act immediately rather than waiting for a clock edge. Pull reset low and the flip-flop clears; pull set low and it presets; do both at once and the datasheet calls the result unstable, since the outputs briefly stop being complements of each other until one input is released. The clock is positive-edge triggered: whatever is on the data pin at the instant the clock rises is what the flip-flop latches, and nothing it does in between edges matters at all. That single behavior, one bit remembered from one edge, is the entire building block a binary counter is made from: feed a flip-flop’s complementary output back into its own clock and it divides whatever is driving it by two, and chaining a few of them is how the ripple counter template on this site counts.

Family
Logic
Pins
14
Pins

14 pins

Named as the editor names them, so a wire lands where you expect it.

Input8

  • 1RD
  • 1D
  • 1CP
  • 1SD
  • 2SD
  • 2CP
  • 2D
  • 2RD

Output4

  • 1Q
  • 1QN
  • 2QN
  • 2Q

Input or output2

  • GND
  • VCC
How to use it

How to wire a 74HC74 as a binary counter

The 74HC74 holds two D flip-flops. Each one copies D to Q on a rising edge of its clock, CP. Tie D to its own Q-bar (QN) and every clock edge flips it, which divides the clock by two. Feed one flip-flop’s Q-bar into the next one’s clock and the outputs count in binary.

The circuit here is two 74HC74s, four flip-flops, counting from 0 to 15 on four LEDs at four steps a second. The set (SD) and reset (RD) pins are active low, so all of them are tied to 5 V; left floating, they can set or clear a flip-flop at random.

Part pin
Board pin
VCC (pin 14), every SD and RD
5 V
GND (pin 7)
GND
1D (pin 2)
1QN (pin 6), so it toggles
1CP (pin 3)
The 4 Hz clock
1QN (pin 6)
2CP (pin 11), the next stage’s clock
1Q, 2Q and the next chip’s
An LED each, through 220 ohms

Take Q instead of Q-bar into the next clock and the counter counts down: that one wire decides the direction.

Binary counterlive0.000 s 0.00x
Click to open it in the editor
This is the simulator itself, running here. Click anything to open it in the editor.
How it is modeled

What is true about the 74HC74 dual flip-flop, here

In its help article’s own words: what the simulation gets right, and where it stops.

74HC74: dual D-type flip-flop with set and reset

Two independent positive-edge-triggered flip-flops. Each has a data input (nD), a clock (nCP), an active-low set (nSD) and an active-low reset (nRD), presenting both nQ and its complement. SD and RD are asynchronous and beat the clock; the clock only matters on a clean Low-to-High edge, and an edge that arrives while the supply is still settling is not counted as one, which is what stops a ripple counter from latching Unknown forever at power-on. A real flip-flop powers up random; this one powers up cleared (Q low), because a divider fed Unknown would never escape it. Propagation delay: 14 ns typical, from CP, SD or RD to Q or QN. See it in: Binary counter.

Not modeled

One typical delay, and nothing around it. Each chip carries a single propagation delay taken from its datasheet's typical column at VCC = 5 V, CL = 15 pF and 25 °C, and uses it for every path through the package. There is no minimum or maximum, no spread between the gates in one chip, no rise or fall time, no output slew and no dependence on supply voltage, load capacitance or temperature, all of which a real 74HC part has, and all of which a datasheet gives ranges for. On the 74HC595 the one figure is the STCP-to-Qn number used for SHCP and MR to Q7S as well, which the datasheet lists a nanosecond or two apart.

No setup, hold or pulse-width checks. The 74HC74 and the 74HC595 take a clock edge whenever they see one; nothing here refuses data that changed too close to the edge or a clock pulse that was too narrow, and nothing warns about it. A real part would metastable or simply miss.

No supply current, no output current limit and no bus contention damage. An output driving into another output is resolved as two drivers on one net; nothing gets hot.

Sequential parts power up cleared rather than random, because a toggle divider fed Unknown never escapes it. See how faithfully a part behaves.

From The 74HC logic family, in full.

Projects

See the 74HC74 dual flip-flop in a project

One built-in project uses it. It opens in the editor, already wired.

Wire up the 74HC74 dual flip-flop

Open the editor and push it into the breadboard. It is free, and it runs on your own machine.