74HC74 dual flip-flop
Two D flip-flops with preset and clear. Divide a clock with one.
- 14 pins
Every one of its 14 pins
What it does
The 74HC74 packages two independent D-type flip-flops, each with a data input, a clock, and an active-low set and reset that both act immediately rather than waiting for a clock edge. Pull reset low and the flip-flop clears; pull set low and it presets; do both at once and the datasheet calls the result unstable, since the outputs briefly stop being complements of each other until one input is released. The clock is positive-edge triggered: whatever is on the data pin at the instant the clock rises is what the flip-flop latches, and nothing it does in between edges matters at all. That single behavior, one bit remembered from one edge, is the entire building block a binary counter is made from: feed a flip-flop’s complementary output back into its own clock and it divides whatever is driving it by two, and chaining a few of them is how the ripple counter template on this site counts.
What is true about the 74HC74 dual flip-flop, here
74HC74: dual D-type flip-flop with set and reset
Two independent positive-edge-triggered flip-flops. Each has a data input (nD), a
clock (nCP), an active-low set (nSD) and an active-low reset (nRD), presenting
both nQ and its complement. SD and RD are asynchronous and beat the clock; the
clock only matters on a clean Low-to-High edge, and an edge that arrives while the
supply is still settling is not counted as one, which is what stops a ripple counter
from latching Unknown forever at power-on. A real flip-flop powers up random; this
one powers up cleared (Q low), because a divider fed Unknown would never escape it.
Propagation delay: 14 ns typical, from CP, SD or RD to Q or QN. See it
in: Binary counter.
Not modeled
One typical delay, and nothing around it. Each chip carries a single propagation
delay taken from its datasheet's typical column at VCC = 5 V, CL = 15 pF and
25 °C, and uses it for every path through the package. There is no minimum or maximum,
no spread between the gates in one chip, no rise or fall time, no output slew and no
dependence on supply voltage, load capacitance or temperature, all of which a real
74HC part has, and all of which a datasheet gives ranges for. On the 74HC595 the one
figure is the STCP-to-Qn number used for SHCP and MR to Q7S as well, which
the datasheet lists a nanosecond or two apart.
No setup, hold or pulse-width checks. The 74HC74 and the 74HC595 take a clock edge whenever they see one; nothing here refuses data that changed too close to the edge or a clock pulse that was too narrow, and nothing warns about it. A real part would metastable or simply miss.
No supply current, no output current limit and no bus contention damage. An output driving into another output is resolved as two drivers on one net; nothing gets hot.
Sequential parts power up cleared rather than random, because a toggle divider fed Unknown never escapes it. See how faithfully a part behaves.
From The 74HC logic family, in full.
See the 74HC74 dual flip-flop in a project
Where it turns up in a lesson
In the twelve week course
In a learn article
The rest of the bench
Every one of these is drawn and simulated the same way.
Wire up the 74HC74 dual flip-flop
Open the editor and push it into the breadboard. It is free, and it runs on your own machine.