D flip-flop (ideal)

One bit of memory with no chip behind it: a D flip-flop, plain or with set and reset.

It is the companion to the ideal gate and the ideal inverter. It needs no power and drives its outputs from nowhere, the way clock does. There are two: the plain D flip-flop, and the D flip-flop with set and reset, which adds S and R. A Wokwi project's wokwi-flip-flop-d and wokwi-flip-flop-dsr import as these.

Pins

Pin	What it does
D	Data input, read on the clock's rising edge.
CLK	Clock. A low-to-high change copies D to Q.
Q	The bit it holds.
QN	The opposite of Q (drawn Q̅).
S	Set, on the one with set and reset. High makes Q 1 at once, whatever the clock does.
R	Reset, on the one with set and reset. High makes Q 0 at once.

Properties

None.

What the model gets right

It is positive-edge triggered: only a clean low-to-high change on CLK moves it, and Q changes 10 ns later. A clock that comes up from unknown, or an unknown D on an edge, makes Q and QN unknown rather than guessing. S and R win over the clock, and both high at once drives Q and QN high together, as the 74HC74 does with both of its asserted. Wire QN back to D and it divides the clock by two.

It powers up cleared, Q low and QN high, so a counter built from these starts at zero without a reset.

What it does not model

No supply pins and no unpowered state, no setup or hold time, no metastability, and a flat 10 ns delay that comes from nowhere. S and R are active high here; on a real 74HC74 they are active low. An S or R left unconnected counts as not asserted. For a real chip with a supply and a datasheet delay, see the 74HC logic family, which includes the 74HC74.

Common mistakes

Expecting Q to follow D while the clock sits high. It only looks at D on the rising edge, which is the whole point of a flip-flop.

See it in action

Flip-flop lab clocks two of these and a multiplexer on three LEDs. Browse /templates for more.