NE555 timer
The real 555, astable or monostable, with the timing the capacitor gives it.
- 8 pins
Every one of its 8 pins
GND while the output is low.What it does
The NE555 is the timer chip in every beginner’s kit, and it has no clock of its own at all. Inside it are three equal resistors from the supply to ground, setting two comparator trip points at one third and two thirds of the supply, an internal flip-flop, an open-collector discharge transistor and an output stage; every timing interval it produces comes entirely from the resistor and capacitor a circuit wires around it. Below about 4.5 volts on the supply the chip is unpowered and its output pins sit high, not driving anything, exactly like a chip that has not been plugged in. Comparator crossings reach the output 100 nanoseconds later, the datasheet’s own typical figure, and the control pin genuinely moves both trip points if something is wired to it, rather than being decorative. The astable and monostable circuits people build around this chip are entirely resistor-and-capacitor math; the chip itself only compares and switches.
What is true about the NE555 timer, here
What is modeled
CTRL really is the control pin: the chip drives it with its own internal divider,
so a decoupling capacitor there behaves as it does on the bench, and forcing a
voltage onto CTRL genuinely moves both trip points. Below 4.5 V the chip is not
running and OUT/DIS go high impedance, the way an unplugged chip would.
OUT's high is a diode drop and a transistor drop below the rail (about 3.3 V on
a 5 V supply) because it is a real bipolar totem pole, not an idealized rail-to-rail
driver. The timing accuracy is the capacitor's, not the chip's, and the capacitor is
solved by the matrix rather than stepped: a textbook astable measures 0.05% fast
against 1.44 / ((RA + 2 RB) C) at 4.7 k, 10 k and 47 k of RB alike, held by a test
in crates/parts/src/parts/ne555.rs.
Not modeled
The monostable used to run about 1.7% short and does not now. A textbook one-shot
on 10 k and 10 uF should run for RC ln 3 = 109.8 ms; until September 17, 2026 it ran
for 108.0, and it now runs for 109.8, within a twentieth of a percent, the same figure
the astable holds. The fault was never the 555: it was in the analog solver, which ran
one integration step ahead of the rest of the simulation, so anything that happened
inside that step (a button contact bouncing, for instance, which is exactly how a
one-shot is started) moved the clock back to the event without moving the capacitor's
charge back with it. The capacitor kept a step's worth of charge it had not been given
the time to collect, once per bounce. It is fixed, and both the monostable and the
astable are now held to 1% by tests that run the real circuits.
The discharge transistor's 10 ohms is not in the textbook formula, and it is in
this model. Where RA is small (a 1 k RA against a 10 k RB), that 10 ohms moves
the frequency about 1% below what 1.44 / ((RA + 2 RB) C) says. The model is right
and the formula is the approximation, but a lesson that checks the formula to better
than a percent should know which of the two it is testing.
The output levels are fixed numbers rather than load-dependent ones: the high is
always VCC − 1.7 V and the low always 0.1 V, where a real bipolar 555's drops depend
on how much current the pin is passing. The comparator delay is a flat 100 ns from a
crossing to the pin, inertial, which is the datasheet's output rise and fall time
standing in for the whole path. Below 4.5 V of supply the chip simply stops rather
than degrading, and there is no supply current, no internal noise, no temperature
drift of the trip points, and no CMOS-variant (7555) behavior.
From NE555 timer, in full.
See the NE555 timer in a project
Where it turns up in a lesson
In the twelve week course
In a learn article
The rest of the bench
Every one of these is drawn and simulated the same way.
Wire up the NE555 timer
Open the editor and push it into the breadboard. It is free, and it runs on your own machine.