Arduino Mega 2560 board contract (Phase 9)

The Mega 2560 is the Arduino for a project that ran out of pins. One kernel component (mega2560 in crates/parts) wraps an ATmega2560 SoC model (crates/atmega2560) on the same AVR core as the Uno (crates/avr-core). The core is shared; the chip around it is not. This document is the contract, and it wins over any comment in the code.

The catalog type is mega2560 (Arduino Mega 2560 R3). Where a section says "as docs/uno.md", that document is the contract for that part.

1. Board pins (catalog order)

Top view, the USB-B socket and the barrel jack on the left edge. The shield headers along the long edges are an Uno's, hole for hole, including the Uno's 0.16 inch gap between the two blocks of the digital header. The 2x18 block of extra digital pins stands on the right-hand short edge.

Top row, left to right (26 holes): SCL, SDA, AREF, GND, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 14, 15, 16, 17, 18, 19, 20, 21.

Bottom row, left to right (23 holes): IOREF, RESET, 3V3, 5V, GNDb, GNDc, VIN, A0 to A15.

The 2x18 block, row by row from the board's long edge inwards (34 holes): 22/23, 24/25, ... 52/53, then 5Vb/GNDd.

83 pins. The two ICSP headers are not pins.

Port mapping, which is the thing this board's pin table exists for. It is not tidy, and it is the real board's:

pins	port
0, 1	PE0, PE1
2, 3	PE4, PE5
4	PG5
5	PE3
6 to 9	PH3 to PH6
10 to 13	PB4 to PB7
14, 15	PJ1, PJ0
16, 17	PH1, PH0
18, 19	PD3, PD2
20, 21	PD1, PD0
22 to 29	PA0 to PA7
30 to 37	PC7 down to PC0
38	PD7
39 to 41	PG2, PG1, PG0
42 to 49	PL7 down to PL0
50 to 53	PB3 down to PB0
A0 to A7	PF0 to PF7
A8 to A15	PK0 to PK7

There is no port I. Ports A to F and H to L are eight bits; port G is six (PG0 to PG5), and the top two bits read 0 and ignore writes.

Electrical:

• Every GPIO drives push-pull at 5 V through R_STRONG, sits high-Z, or pulls up through 35 k, exactly as docs/uno.md section 1 sets out. An input reads high at 2.5 V; a floating or contended net reads 0.
• SCL/SDA beside AREF are the same two pieces of metal as pins 21 and 20. That is the R3 change to the shield header. Both holes of each pair carry what the pin is driving plus whatever the other side's net is doing, through R_STRAP, exactly as the Uno's A4/SDA pair does.
• 5V, 5Vb and IOREF drive 5 V at R_SUPPLY; 3V3 drives 3.3 V; GND, GNDb, GNDc and GNDd drive 0 V. VIN is an input the board ignores: it is always USB powered.
• RESET carries a 10 k pull-up to 5 V. Pulling it below 2.5 V holds the CPU in reset; letting go is an external reset, which is what MCUSR reports.
• AREF is only ever read, never driven. With an internal reference selected the pin is left alone.
• Pin 13 has the on-board L LED through 1 k to ground.
• A0 to A15 are ordinary digital pins as well as analog inputs, unlike the Nano's A6 and A7.

2. Memory map

flash	256 KB, 128 K instruction words, PC 17 bits
SRAM	8 KB at 0x0200 to 0x21FF, RAMEND = 0x21FF
EEPROM	4 KB
registers	32 at 0x0000 to 0x001F
I/O	0x0020 to 0x005F, reachable with IN/OUT
extended I/O	0x0060 to 0x01FF, reachable only with LD/ST

Three things follow from a quarter-megabyte flash and a 17-bit PC, and the core handles all three:

• RAMPZ (0x5B) extends Z for ELPM and SPM. ELPM Rd, Z+ carries out of Z into RAMPZ, so one pointer walks the whole of flash.
• EIND (0x5C) extends the target of EIJMP and EICALL.
• CALL, RCALL, ICALL, EICALL, RET and RETI push and pop a three-byte return address, and an interrupt does the same, so a stack frame here is one byte deeper than an Uno's.

SP is 0x21FF out of reset.

3. Peripherals

Addresses are data addresses. The whole of this section is the ATmega2560 data sheet's map, not a convenience.

3.1 Ports

PINx, DDRx, PORTx consecutive, one group per port: A 0x20, B 0x23, C 0x26, D 0x29, E 0x2C, F 0x2F, G 0x32, H 0x100, J 0x103, K 0x106, L 0x109. MCUCR (0x55) bit 4 is PUD, which disables every pull-up at once.

Writing 1 to a PINx bit toggles the corresponding PORTx bit, as on the Uno.

3.2 Timers

Six. Timers 0 and 2 are eight-bit with two compare channels; timers 1, 3, 4 and 5 are sixteen-bit with three compare channels each, A, B and C.

timer	base	kind
0	TCCR0A 0x44	8-bit, 2 channels
1	0x80	16-bit, 3 channels
2	TCCR2A 0xB0	8-bit, 2 channels, async
3	0x90	16-bit, 3 channels
4	0xA0	16-bit, 3 channels
5	0x120	16-bit, 3 channels

A sixteen-bit timer's registers run TCCRnA, TCCRnB, TCCRnC, gap, TCNTnL, TCNTnH, ICRnL, ICRnH, OCRnAL, OCRnAH, OCRnBL, OCRnBH, OCRnCL, OCRnCH from the base. The high-byte temporary register is shared across all of them, as the data sheet says.

Interrupt masks are TIMSK0 0x6E, TIMSK1 0x6F, TIMSK2 0x70, TIMSK3 0x71, TIMSK4 0x72, TIMSK5 0x73; flags are TIFR0 0x35 through TIFR5 0x3A.

Every waveform mode of docs/uno.md section 3.2 is here, in all six timers, and the compare outputs reach their pads. OC0A and OC1C are both PB7, which is pin 13: whichever is enabled first owns the pad, and only the owner can release it.

3.3 ADC

Sixteen external channels. ADMUX 0x7C, ADCSRA 0x7A, ADCSRB 0x7B, ADCL/ADCH 0x78/0x79, DIDR0 0x7E, DIDR1 0x7F, DIDR2 0x7D.

The channel number is five bits, and the fifth is not in ADMUX: it is MUX5, bit 3 of ADCSRB. So channel = (ADCSRB.MUX5 << 4) | (ADMUX & 0x1F). Channels 0 to 7 are A0 to A7; with MUX5 set, 0 to 7 are A8 to A15.

REFS1:0 selects the reference: 0 = AREF, 1 = AVcc (5 V), 2 = the 1.1 V internal bandgap, 3 = the 2.56 V internal. The Uno has no 2.56 V reference; this part does.

Ten-bit result, right adjusted unless ADLAR is set. Conversion timing is the Uno's: 13 ADC clocks for a normal conversion, 25 for the first after ADEN, at the prescaled clock ADPS2:0 selects.

3.4 USARTs

Four. Bases 0xC0, 0xC8, 0xD0 and 0x130, each UCSRnA, UCSRnB, UCSRnC, gap, UBRRnL, UBRRnH, UDRn. Bit names are the Uno's.

USART0 is the host channel: what a program writes to UDR0 reaches the serial monitor, and what the monitor sends arrives in UDR0. It does not drive PE0 and PE1.

USART1, USART2 and USART3 drive their pads. Setting TXEN takes the TX pin over regardless of its DDRx bit and sends a real 8N1 frame: start bit low, eight data bits least significant first, stop bit high, one bit time each at the rate UBRRn sets. Setting RXEN takes the RX pin over as an input and samples it in the middle of each bit. A wire between two of these pins carries bytes at the speed the sketch asked for, and a mismatched pair produces mojibake, as it would on the bench.

TX and RX pins: USART1 PD3/PD2, USART2 PH1/PH0, USART3 PJ1/PJ0.

3.5 External and pin-change interrupts

Eight external interrupts, INT0 to INT7, on PD0 to PD3 and PE4 to PE7. The sense bits are split: INT0 to INT3 in EICRA (0x69), INT4 to INT7 in EICRB (0x6A), two bits each. Mask EIMSK 0x3D, flags EIFR 0x3C.

The Arduino numbering is not the hardware's: interrupt 0 is pin 2, which is INT4; interrupts 2 to 5 are pins 21 down to 18, which are INT0 to INT3. INT6 and INT7 are on PE6 and PE7, which the board does not bring out, so nothing can be attached to them.

Pin change: three groups rather than the Uno's three ports. PCINT0 is port B, PCINT1 is PE0 plus PJ0 to PJ6, PCINT2 is port K. PCICR 0x68, PCIFR 0x3B, masks PCMSK0 0x6B, PCMSK1 0x6C, PCMSK2 0x6D.

3.6 Sleep and EEPROM

SMCR 0x53 holds SE and the sleep mode bits. SLEEP with SE set parks the core until an interrupt, and a parked core costs the simulator nothing.

EEPROM is 4 KB through EEARH/EEARL, EEDR and EECR, as docs/uno.md section 3.6.

3.7 Vectors

57 vectors, two words each, because only JMP reaches all of a 256 KB flash. Vector n is at word address 2n. The numbering is the data sheet's: 0 reset, 1 to 8 INT0 to INT7, 9 to 11 PCINT0 to PCINT2, 12 watchdog, 13 to 15 timer 2, 16 to 20 timer 1, 21 to 23 timer 0, 24 SPI, 25 to 27 USART0, 28 analog comparator, 29 ADC, 30 EEPROM ready, 31 to 35 timer 3, 36 to 38 USART1, 39 TWI, 40 SPM ready, 41 to 45 timer 4, 46 to 50 timer 5, 51 to 53 USART2, 54 to 56 USART3.

4. Host channel

host = "utf-8 bytes on USART0", as the Uno.

5. Time model and the part

16 MHz, 10 us slices, 160 cycles a slice, pin changes reported at their exact cycle offset within the slice and turned into drive_after calls at the same offsets. SLEEP parks the core and the part then schedules the next wake at whatever the chip is waiting for rather than every 10 us. All of this is docs/uno.md section 5 unchanged.

Probe: bit 0 running, bit 1 sleeping, bit 2 the on-board LED on pin 13, bit 3 TX activity in the last 20 ms, bit 4 RX activity; 0 with no program. Poke: 2 = press RESET, 3 = release.

A crash (an illegal opcode, a jump past the end of flash, a stack that ran away) stops the core, leaves the pins where they were, and writes one line on the host channel naming the fault and the PC, in five hex digits because this part's PC needs them.

6. Firmware (firmware/mega/)

Its own runtime, because the part really is different. Five files are the Uno's, compiled again for this target rather than copied, because nothing in them depends on how many ports or timers the chip has: support.S, src/support.c, src/format.c, src/math.c, src/print.cpp and src/main.cpp. Everything else is this board's: crt0.S (57 vectors, a stack at 0x21FF, ELPM with RAMPZ for the .data copy), link.ld, the 70-entry pin table, the timer tick, the sixteen-channel ADC, the four USARTs and the external interrupts.

NUM_DIGITAL_PINS is 70, NUM_ANALOG_INPUTS is 16, A0 to A15 are pins 54 to 69, LED_BUILTIN is 13, MOKXI_BOARD is "mega2560".

Examples under firmware/mega/examples/<name>/sketch.ino, built to web/public/firmware/mega/<name>.elf with web/public/firmware/mega/index.json: blink (pin 13), serial, ports (all four USARTs, each of the three header ones jumpered back to its own RX), chaser (twelve LEDs on pins 22 to 33, one pin each, with no shift register).

The index's program field is "elf32 avr atmega2560", and the catalog entry says the same. Unlike the Nano's, this string differs from the Uno's because the ELF really does: different chip, different register map, different vector table.

7. What is not modeled

• The USB-to-serial bridge, the 16U2. Serial reaches the serial monitor through the host channel, and pins 0 and 1 stay plain GPIO.
• SPI, TWI/I2C, the watchdog, the analog comparator and the JTAG interface. Their registers read back what was written; nothing happens.
• Shields as physical parts. Wire the same circuit on the breadboard instead.
• The Arduino IDE library ecosystem. The runtime here is ours and Arduino-shaped, not the Arduino core.
• The Mega ADK and the older Mega 1280. This is the Mega 2560 R3.

8. What this model is sure of, and what it is not

Taken from the data sheet. Every address, bit position and reset value in section 3 is from the ATmega640/1280/1281/2560/2561 Data Sheet, in data-space numbering. The eleven ports, the six timers, the four USARTs, the sixteen ADC channels and their ADCSRB/MUX5 split, the eight external interrupts and the pin-change groups are the data sheet's, and so is the 256 KB of flash with its three-byte program counter and EIND. The board's own numbers (the header order in section 1, the LED on pin 13 (PB7), and which chip pin each of the 54 digital and 16 analog pins is) are the Mega 2560 R3's schematic.

Modeled, but not held to the data sheet's numbers. Everything in docs/uno.md section 7's middle group applies here unchanged, because it is the same core and the same peripheral shapes: an ADC that is round(1023 × Vin / Vref) with no sample-and-hold, no nonlinearity, no noise and no offset; an exact 16 MHz clock with no tolerance, drift or jitter; three pad states and a threshold, with a 35 kΩ pull-up, no hysteresis, no rise time and no current limit; an ideal supply that cannot sag; a one-microsecond start-up where a real board spends 65 ms in its bootloader; and a 10 us slice with the core stepped one instruction at a time inside it.

Deliberately absent, as section 7 lists: the 16U2 USB-to-serial bridge, SPI, TWI/I2C, the watchdog, the analog comparator, the JTAG interface, shields as physical parts, and the Arduino core's library ecosystem. Their registers read back what was written and nothing happens. This is the Mega 2560 R3, not the ADK and not the older 1280.