Graded digital logic labs: find a gate from its truth table, build a half adder and a 2-to-1 multiplexer, divide a clock with a D flip-flop, count to ten.
On the syllabus
Truth tables and the six two-input gates
The half adder: sum and carry
The 2-to-1 multiplexer
The D flip-flop and divide-by-two
Counters: the CD4017 decade counter
You will be able to
Read a truth table off a timing diagram and name the gate.
Build a half adder and a multiplexer from gates.
Use a D flip-flop to divide a clock, and predict the output frequency.
Measure a decade counter’s output period and pulse width.
The first challenge is free. The rest, the viva and the certificate are part of Pro, and everything is here to read.
Graded challenges
Values like 4.7k, 100n or 2.2u are fine. Readings are the number only, in the unit shown. Every check measures the simulation, not a bench: ideal parts within their models, no noise.
1. Name the gate from its truth table
A truth table lists the output for every input combination. Each of the six two-input gates has its own pattern, so four rows are enough to name it.
FormulaCount the rows that give 1, then see which ones they are
Worked exampleA table of 1, 0, 0, 0 for 00, 10, 01, 11 is high only when both inputs are 0: that is NOR. A table of 1, 1, 1, 0 is NAND.
On the scope or meterThe LED lights on the rows that give 1. The check reads each row at a set time in the first 10 ms.
Your task
Two clocks drive gate G1: A at 200 Hz and B at 100 Hz. Both start low, so in the first 10 ms the inputs run through 00, 10, 01 and 11.
Set G1’s function so its output follows this table: 00 gives 0, 10 gives 1, 01 gives 1, 11 gives 0. An LED shows the output.
2. Build a half adder
Adding two one-bit numbers gives a two-bit result: a sum bit and a carry bit. 0 + 0 = 00, 0 + 1 = 01, 1 + 0 = 01, 1 + 1 = 10.
FormulaA + B = (carry, sum)
Worked exampleIn decimal, 7 + 5 = 12: you write 2 and carry 1. In binary, 1 + 1 works the same way: write 0, carry 1.
On the scope or meterTwo LEDs read as a binary number. With both inputs high only the carry LED is on.
Your task
The same two clocks are the bits A and B. Gate G1 makes the sum bit and gate G2 the carry bit, each with an LED.
Set both gates so that A + B appears on the two LEDs: carry and sum, as a two-bit binary number.
3. Finish a 2-to-1 multiplexer
A multiplexer is a switch made of logic. Each data input gets a gate that only lets it through when its select condition is true; a final gate joins the two paths. Writing it as products added together is called a sum of products.
FormulaY = (A · S̄) + (B · S)
Worked exampleWith S = 0, the B path is blocked and the A path passes A, so Y = A. With S = 1 the paths swap and Y = B.
On the scope or meterThe LED follows the fast clock A for the first 5 ms, while S is low, then the slower clock B for the next 5 ms.
Your task
Three clocks: A at 400 Hz, B at 200 Hz and the select line S at 100 Hz, so 10 ms holds all eight rows.
G1 is wired as NOT S (a NAND with both inputs on S). G2 combines A with NOT S, G3 combines B with S, and G4 combines G2 and G3 into the output Y.
Set G2, G3 and G4 so Y follows A while S is 0 and B while S is 1.
4. Divide a clock with a D flip-flop
A D flip-flop copies D to Q on each rising clock edge. Feed QN back to D and every edge flips Q. Q goes through one full cycle every two clock cycles.
Formulaf(Q) = f(clock) / 2
Worked exampleAn 800 Hz clock gives Q at 400 Hz. Two flip-flops in a chain give 200 Hz: each stage halves it again.
On the scope or meterQ is a square wave at half the clock rate, changing only on rising clock edges.
Your task
A 74HC74 D flip-flop has its QN output wired back to D, so it toggles on every rising clock edge. An LED shows Q.
Set the clock so Q runs at 250 Hz: one cycle every 4 ms, within 2%.
5. Read a decade counter
A CD4017 has ten outputs and moves a single high from one to the next on each clock. Q0 is high for one clock out of every ten.